S3CC40D/FC40D_UM_REV1.20
INSTRUCTION SET
6-5
LD REGISTER, DATA MEMORY / LD DATA MEMORY, REGISTER
LDW Rn, @[SP+edisp:9] / LDW @[SP+edisp:9], Rn
The instructions transfer 16-bit data between a general register Rn and the memory location at the address of
(SP+edisp:9). Note SP is another name of A15. edisp:9 is an even positive displacement from 0 to 510. edisp:9 is
encoded into an 8-bit displacement value in the instruction map because the LSB is always 0. When the address
is calculated, the 8-bit displacement field is shifted to the left by one bit, and then the result is added to the value
of SP. Even if the address might be specified as odd in assembly mnemonic, the LSB of the address should be
truncated to zero for word alignment.
LDW Rn, @[Ai+edisp:5] / LDW @[Ai+edisp:5], Rn
The instructions transfer 16-bit data between a general register Rn and the memory location at the address of
(Ai+edisp:5). edisp:5 is an even positive displacement from 0 to 30. edisp:5 is encoded into an 4-bit displacement
value in the instruction map because the LSB is always 0. When the address is calculated, the 4-bit displacement
field is shifted to the left by one bit, and then the result is added to the value of Ai. Even if the address might be
specified as odd in assembly mnemonic, the LSB of the address should be truncated to zero for word alignment.
LDW Rn, @[Ai+disp:16] / LDW @[Ai+disp:16], Rn
The instructions transfer 16-bit data between a general register Rn and the memory location at the address of
(Ai+disp:16). disp:16 is an positive displacement from 0 to FFFFh. If the address is odd, the LSB of the address is
set to zero for word alignment.
LDW Rn, @[Ai+Rj] / LDW @[Ai+Rj], Rn
The instructions transfer 16-bit data between a general register Rn and the memory location at the address of
(Ai+Rj). The value of Rj is zero-extended to 22-bit value. If the address is odd, the LSB of the address is set to
zero for word alignment.
LDW An, @[Ai+edisp:5] / LDW @[Ai+edisp:5], An
The instructions transfer 22-bit data between an address register An and the memory location at the address of
(Ai+edisp:5). edisp:5 is an even positive displacement from 0 to 30. edisp:5 is encoded into an 4-bit displacement
value in the instruction map because the LSB is always 0. When the address is calculated, the 4-bit displacement
field is shifted to the left by one bit, and then the result is added to the value of Ai. Even if the address might be
specified as odd in assembly mnemonic, the LSB of the address should be truncated to zero for word alignment.
LDW An, @[Ai+disp:16] / LDW @[Ai+disp:16], An
The instructions transfer 22-bit data between an address register An and the memory location at the address of
(Ai+disp:16). disp:16 is an positive displacement from 0 to FFFFh. If the address is odd, the LSB of the address is
set to zero for word alignment.
LDW An, @[Ai+Rj] / LDW @[Ai+Rj], An
The instructions transfer 22-bit data between an address register An and the memory location at the address of
(Ai+Rj). The value of Rj is zero-extended to 22-bit value. If the address is odd, the LSB of the address is set to
zero for word alignment.