INSTRUCTION SET
S3CC40D/FC40D_UM_REV1.20
BRANCH INSTRUCTIONS
CalmRISC16 has 2 classes of branch instructions: with a delay slot and without a delay slot. If a delay slot is filled
with a useful instruction (or an instruction which is not NOP), then the performance degradation due to the control
dependency can be minimized. However, if the delay slot cannot be used, then it should be NOP instruction,
which can increase the program code size. In this case, the corresponding branch instruction without a delay slot
can be used to avoid using NOP.
Some instructions are not permitted to be in the delay slot. The prohibited instructions are as follows.
All 2-word instructions
All branch and jump instructions including SWI, RETD, RET_SWI, RET_IRQ, RET
BREAK instructions
When a prohibited instruction is in the delay slot, the operation of CalmRISC16 is undefined or unpredictable.
BSRD eoffset:13
In the instruction, called branch subroutine with a delay slot, the value (PC + 4) is saved into A14 register, the
instruction in the delay slot is executed, and then the program sequence is moved to (PC + 2 + eoffset:13), where
PC is the address of the instruction “BSRD eoffset:13”. The immediate value eoffset:13 is sign-extended to 22-bit
and then added to (PC+2). In general, the 13-bit offset field appears as a label in assembly programs. If the
instruction in the delay slot reads the value of A14, the value (PC+4) is read. The even offset eoffset:13 is
encoded to 12bit signed offset in instruction map by dropping the least significant bit.
BRA/BRAD/BRT/BRTD/BRF/BRFD eoffset:11
In the branch instructions, the target address is (PC + 2 + eoffset:11). The immediate value eoffset:11 is sign-
extended to 22-bit and then added to (PC+2). The “D” in the mnemonic stands for a delay slot. In general, the
11-bit offset field appears as a label in assembly programs. BRA and BRAD instructions always branch to the
target address. BRT and BRTD instructions branch to the target address if T flag is set. BRF and BRFD
instructions branch to the target address if T flag is cleared. BRAD/BRTD/BRFD instructions are delay slot branch
instructions, therefore the instruction in the delay slot is executed before the branch to the target address or the
branch decision is made. The even offset eoffset:11 is encoded to 10-bit signed offset in instruction map by
dropping the least significant bit.
BRA/BRAD EC:2, eoffset:8
In the branch instructions, the target address is (PC + 2 + eoffset:8). The immediate value eoffset:8 is sign-
extended to 22-bit and then added to (PC+2). The EC:2 field indicates one of the 4 external conditions from EC0
to EC3 (input pin signals to CalmRISC16). When the external condition corresponding to EC:2 is set, the program
branches to the target address. BRAD has a delay slot. The even offset eoffset:8 is encoded to 7-bit signed offset
in instruction map by dropping the least significant bit.
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