
S3CC40D/FC40D_UM_REV1.20
EXCEPTIONS
INTERRUPT PRIORITY REGISTERS
(IPR0H/L: 3F000CH/0DH, IPR1H/L: 3F0014H/15H, IPR2H/L: 3F001CH/1DH)
.2
.1
IPR0L, IPR1L,
IPR2L
.3
.4
.5
xx000: X0 > Y0 > Z0 > X1 > Y1 > Z1
x0100: X0 > Y0 > X1 > Z0 > Y1 > Z1
01100: X0 > Y0 > X1 > Y1 > Z0 > Z1
11100: X0 > Y0 > X1 > Y1 > Z1 > Z0
x0010: X0 > X1 > Y0 > Z0 > Y1 > Z1
00110: X0 > X1 > Y1 > Y0 > Z0 > Z1
10110: X0 > X1 > Y1 > Y0 >Z1 > Z0
01010: X0 > X1 > Y0 > Y1 > Z0 > Z1
11010: X0 > X1 > Y0 > Y1 > Z1 >Z0
x1110: X0 > X1 > Y1 > Z1 > Y0 > Z0
xx001: X1 > Y1 > Z1 > X0 > Y0 > Z0
x0101: X1 > Y1 > X0 > Z1 > Y0 > Z0
01101: X1 > Y1 > X0 > Y0 > Z1 > Z0
11101: X1 > Y1 > X0 > Y0 > Z0 > Z1
x0011: X1 > X0 > Y1 > Z1 > Y0 > Z0
00111: X1 > X0 > Y0 > Y1 > Z1 > Z0
10111: X1 > X0 > Y0 > Y1 > Z0 > Z1
01011: X1 > X0 > Y1 > Y0 > Z1 > Z0
11011: X1 > X0 > Y1 > Y0 > Z0 > Z1
x1111: X1 > X0 > Y0 > Z0 > Y1 > Z1
.9
.8
IPR0H, IPR1H,
IPR2H
.10
.11
.12
Not used
.6
.7
.0
Group A
0 = IRR0 > IRR1
1 = IRR1 > IRR0
Gjroup Priority:
.7 .6 .5
0 0 0 = A > B > C
0 0 1 = B > C > A
0 1 0 = A > B > C
0 1 1 = B > A > C
1 0 0 = C > A > B
1 0 1 = C > B > A
1 1 0 = A > C > B
1 1 1 = A > B > C
Group B
0 = IRR2 > (IRR3, IRR4)
1 = (IRR3, IRR4) > IRR2
Subgroup B
0 = IRR3 > IRR4
1 = IRR4 > IRR3
Group C
0 = IRR5 > (IRR6, IRR7)
1 = (IRR6, IRR7) > IRR3
Subgroup C
0 = IRR6 > IRR7
1 = IRR7 > IRR6
IRR7
IRR6
IRR5
IRR4
IRR3
IRR2
IRR1
IRR0
IRR15
IRR14
IRR13
IRR12
IRR11
IRR10
IRR9
IRR8
IRR0L, IRR1L, IRR2L
IRR0H, IRR1H, IRR2H
Group 0 (X0, Y0, Z0)
Group 1 (X1, Y1, Z1)
Group C
Group B
Group A
NOTES:
1.
X, Y, Z represent priority groups (A, B, or C) determined by bits (7, 6, 5)
2.
If bits (7, 6, 5) are (1, 1, 1), then X, Y, Z is corresponded to A, B, C.
3.
If bits (7, 6, 5) are (1, 0, 1), then X, Y, Z is corresponded to C, B, A.
4.
The interrupt priorities are identified in inverse order: The IRR0 group is he highest priority,
and the IRR1 group is the next highest,and the IRR2 group is the lowest.
Figure 4-3. Interrupt Priority Register
4-13