S3CC40D/FC40D_UM_REV1.20
INSTRUCTION SET
6-3
ALUOP REGISTER, REGISTER
ADD/SUB/ADC/SBC/AND/OR/XOR/TST/CMP/CMPU Rn, Ri
The instructions perform an ALU operation of which source operands are a pair of 16-bit general registers. In the
instructions TST/CMP/CMPU, only T flag is updated as the result. In the instructions ADD/ADC/SUB/SBC, the
value of T flag is the carry of the operations, and the value of V flag indicates whether overflow or underflow
occurs. In the instructions AND/OR/XOR/TST, the value of T flag indicates whether the result is zero. “CMP
{GT|GE|EQ}, Rn, Ri” instructions are for signed comparison, and “CMPU {GT|GE}, Rn, Ri” instructions are for
unsigned comparison.
ADD/SUB An, Ri
16-bit general register Ri is zero-extended to 22-bit value. The result is saved in the 22-bit register An. No flag
update occurs.
CMP EQ, An, Ai
The instruction compares two 22-bit registers.
MUL {SS|SU|US|UU}, Rn, Ri
The general registers Rn and Ri can be one of R0 to R7. The instruction multiplies the lower byte of Rn and the
lower byte of Ri, and the 16-bit result is saved in Rn. The optional field, SS, SU, US, and UU, indicates whether
the source operands are signed value or unsigned value. The first letter of the two letter qualifiers corresponds to
Rn, and the second corresponds to Ri. For example, in the instruction “MUL SU, R0, R1”, the 8-bit signed value in
the lower byte of R0 and the 8-bit unsigned value in the lower byte of R1 are multiplied, and the 16-bit result is
saved in R0.
RR/RL/RRC/SR/SRA/SLB/SRB/DT/INCC/DECC/COM/COM2/COMC/EXT Rn
For “DT Rn”(Decrement and Test) and “COM Rn”(Complement) instructions, T flag indicates whether the result is
zero. In the instruction of “EXT Rn”(Sign Extend), no flag update occurs. In all other instructions, carry-out of the
operation is transferred to T flag. In the instruction of DT, INCC, and DECC, V flag indicates whether overflow or
underflow occurs.