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参数资料
| 型号： | SI5338N-AXXXXXGM |
| 厂商： | SILICON LABORATORIES |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 700 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC24 |
| 封装： | 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-8, QFN-24 |
| 文件页数： | 22/42页 |
| 文件大小： | 380K |
| 代理商： | SI5338N-AXXXXXGM |
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Si5338
Rev. 1.0
29
5. I2C Interface
Configuration and operation of the Si5338 is controlled
by reading and writing to the RAM space using the I2C
interface. The device operates in slave mode with 7-bit
addressing
and
can
operate
in
Standard-Mode
(100 kbps) or Fast-Mode (400 kbps) and supports burst
data transfer with auto address increments.
The I2C bus consists of a bidirectional serial data line
(SDA) and a serial clock input (SCL) as shown in
Figure 21. Both the SDA and SCL pins must be
connected to the VDD supply via an external pull-up as
recommended by the I2C specification.
Figure 21. I2C and Control Signals
The 7-bit device (slave) address of the Si5338 consists
of a 6-bit fixed address plus a user-selectable LSB bit as
shown in Figure 22. The LSB bit is selectable using the
optional I2C_LSB pin which is available as an ordering
option for applications that require more than one
Si5338 on a single I2C bus. Devices without the
I2C_LSB pin option have a fixed 7-bit address of 70h
addresses are also possible. See Table 16 for details on
device ordering information with the optional I2C_LSB
pin.
Figure 22. Si5338 I2C Slave Address
Data is transferred MSB first in 8-bit words as specified
by the I2C specification. A write command consists of a
7-bit device (slave) address + a write bit, an 8-bit
register address, and 8 bits of data as shown in
Figure 23. A write burst operation is also shown where
every additional data word is written using an auto-
incremented address.
Figure 23. I2C Write Operation
A read operation is performed in two stages. A data
write is used to set the register address, then a data
read is performed to retrieve the data from the set
address. A read burst operation is also supported. This
is shown in Figure 24.
Figure 24. I2C Read Operation
AC and dc electrical specifications for the SCL and SDA
pins are shown in Table 14. The timing specifications
and timing diagram for the I2C bus are compatible with
the I2C-Bus Standard. SDA timeout is supported for
compatibility with SMBus interfaces.
The I2C bus can be operated at a bus voltage of 1.71 to
3.63 V and is 3.3 V tolerant. If a bus voltage of less than
2.5 V is used, register 27[7] = 1 must be written to
maintain compatibility with the I2C bus standard.
Control
I2C_LSB
I2C_LSB/PDEC/FDEC
OEB/PINC/FINC
0/1
SCL
SDA
I
2C Bus
VDD
Slave Address
(with I2C_LSB Option)
1 1 1 0 0 0 0/1
I2C_LSB pin
0
1
2
3
4
5
6
Slave Address
(without I2C_LSB Option)
1 1 1 0 0 0
0
1
2
3
4
5
6
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
P – STOP condition
From slave to master
From master to slave
Write Operation – Single Byte
S
0 A Reg Addr [7:0]
Slv Addr [6:0]
A Data [7:0]
P
A
Write Operation - Burst (Auto Address Increment)
Reg Addr +1
S
0 A Reg Addr [7:0]
Slv Addr [6:0]
A Data [7:0]
P
A
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
P – STOP condition
From slave to master
From master to slave
Read Operation – Single Byte
S
0 A Reg Addr [7:0]
Slv Addr [6:0]
A P
Read Operation - Burst (Auto Address Increment)
Reg Addr +1
S
1 A
Slv Addr [6:0]
Data [7:0]
P
N
S
0 A Reg Addr [7:0]
Slv Addr [6:0]
A P
S
1 A
Slv Addr [6:0]
Data [7:0]
A
P
N
Data [7:0]
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相关代理商/技术参数 |
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|---|---|
| SI5338N-B01504-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Bulk |
| SI5338N-B01504-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
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