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参数资料
| 型号： | SI5338N-AXXXXXGM |
| 厂商： | SILICON LABORATORIES |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 700 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC24 |
| 封装： | 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-8, QFN-24 |
| 文件页数： | 40/42页 |
| 文件大小： | 380K |
| 代理商： | SI5338N-AXXXXXGM |
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Si5338
Rev. 1.0
7
Phase Increment/Decrement
Update Time
PUPDATE
Pin control2,3
MultiSynth output <18 MHz
Number of periods of
MultiSynth output frequency
—10
12
Periods
Frequency Increment/
Decrement Step Size
fSTEP
R divider not used
1
—
See
Note 2
ppm
MultiSynth range for frequency
increment/decrement
fRANGE
R divider not used
5
—
Fvco/8
MHz
Frequency Increment/
Decrement Update Time
fUPDATE
Pin control2,3
MultiSynth output >18 MHz
——
667
ns
Frequency Increment/
Decrement Update Time
fUPDATE
Pin control2,3
MultiSynth output <18 MHz
Number of periods of
MultiSynth output frequency
—10
12
Periods
Spread Spectrum PP
Frequency Deviation
SSDEV
MultiSynth Output < ~Fvco/8
0.1
—
5.04
%
Spread Spectrum Modulation
Rate
SSDEV
MultiSynth Output < ~Fvco/8
30
—
635
kHz
Table 5. Performance Characteristics (Continued)
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Notes:
1. Outputs at integer-related frequencies and using the same driver format. See "3.10.3. Programmable Initial Phase
Offset" on page 25.
2. The maximum step size is only limited by the register lengths; however, the MultiSynth output frequency must be kept
between 5 MHz and Fvco/8.
3. Update rate via I2C is also limited by the time it takes to perform a write operation.
4. Default value is 0.5% down spread.
5. Default value is ~31.5 kHz.
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相关代理商/技术参数 |
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| SI5338N-B01504-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Bulk |
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