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| 型号： | SI5338N-AXXXXXGM |
| 厂商： | SILICON LABORATORIES |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 700 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC24 |
| 封装： | 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-8, QFN-24 |
| 文件页数： | 36/42页 |
| 文件大小： | 380K |
| 代理商： | SI5338N-AXXXXXGM |
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Si5338
Rev. 1.0
41
DOCUMENT CHANGE LIST
Revision 0.1 to 0.2
Updated block diagram to show Rn output divider
and PLL bypass mode
Updated pin description to include FDBK±
Updated Table 3. DC Characteristics
Updated Table 12. Jitter Specifications
Added Supply Current vs. Output Frequency
Updated package outline specification
Clarified input clock configuration register settings
Updated DRV_INVERTn[1:0] settings
Added PLL bypass mode
Added LOS_FDBK description
Added additional detail to phase increment/
decrement and frequency increment/decrement
descriptions
Clarified output driver powerdown options
Clarified entry to self-calibration mode
Updated ordering guide
Revision 0.2 to 0.3
Changed minimum output clock frequency from
5MHz to 1MHz.
Updated slew rates.
Updated " Features" on page 1.
Updated Table 6, “Input and Output Clock
Deleted Table 12, “Output Driver Slew Rate Control”.
Revision 0.3 to 0.5
Major editorial changes to all sections to improve
clarity
Completed electrical specification tables with final
characterization results
Revised the maximum input and output frequencies
from 700 MHz to 710 MHz
Improved jitter specifications to reflect updated
characterization results
Added new Si5338N/P/Q ordering codes
Added typical application diagrams
Added an application section to highlight the
flexibility of the Si5338 in various timing functions
Added a configuration section to clarify configuration
options
Revision 0.5 to 0.55
Editorial changes to section 3.5 “Configuring the
Si5338” to improve clarity on ordering custom
Si5338 and on configuring “blank” Si5338.
Added pin numbers to device package drawings.
Updated ordering information to include evaluation
boards.
Updated first page description and applications
Added
JC to specification tables.
Added GbE RM jitter specification with 1.875–
20 MHz integration band.
Revision 0.55 to 0.6
Changed output duty cycle to 45–55%.
All I2C address now in binary.
Changed ordering information to reflect 710 MHz
limit.
Info on POR and soft reset added.
Updated Figure 15 on page 26.
Added register section.
Update programming procedure in “3.5. Configuring
the Si5338” to improve robustness.
Updated Figure 9 to include the entire programming
procedure.
Detectors" on page 17 to show the location of the
LOS detector circuits.
Updated input circuit diagrams in "3.2. Input Stage"
Update block diagrams with new input circuit
diagrams.
Revision 0.6 to 0.65
page 21 for consistency with register description.
Revision 0.65 to 1.0
Expanded PCI jitter specifications in Table 12.
Moved “Si5338 Registers” section to AN411.
Revised CMOS output currents down for each
CMOS driver that is active in Table 3.
Clarified CMOS output loads in Table 3
Added peak reflow temperature and footnote in
Added sticky and mask register info in "3.6. Status
Added more information to Table note about CMOS
outputs and jitter in Table 12.
Changed all reference of MultiSynth Mn to MSn
Added "11. Top Marking" on page 39.
Reworded 3.5.2 and 3.5.3 for clarity.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SI5338N-B01504-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Bulk |
| SI5338N-B01504-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| SI5338N-B01552-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Bulk |
| SI5338N-B01552-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| SI5338N-B01598-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Bulk |
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