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参数资料
| 型号： | SME1430LGA-480 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 480 MHz, RISC PROCESSOR, CBGA587 |
| 封装： | CERAMIC, LGA-587 |
| 文件页数： | 13/60页 |
| 文件大小： | 646K |
| 代理商： | SME1430LGA-480 |
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SME1430LGA-360
SME1430LGA-440
SME1430LGA-480
Highly Integrated 64-Bit RISC; L2-Cache, DRAM, PCI Interfaces
UltraSPARC-IIi CPU
May 1999
Sun Microsystems, Inc
PCI interface
Symbol
Volts
Type
Signal
Transitions
Aligned with:
Name and Function
AD[31:0]
3.3 V
(All)
I/O
PCI_CLK
Address/Data; multiplexed on same PCI pins.
CBE_L[3:0]
I/O
Bus Command and Byte Enables; multiplexed on same PCI pins
PAR
I/O
Parity; even parity across AD[31:0] and CBE_L[3:0]
DEVSEL_L
STS [1]
1. Sustained Tri-State. STS is an active low tri -state signal owned and driven by one and only one agent at a time. The agent that drives an STS pin
low must drive it high for at least one clock before letting it oat. A new agent cannot start driving an STS signal any sooner than one clock after
the previous owner tri-states it. A pullup is required to sustain the inactive state until another agent drives it, and must be provided by the
motherboard or module.
Device Select. Indicates the driving device has decoded the
address of the target of the current access; as input, indicates
whether any device has been selected
FRAME_L
STS
Cycle Frame; driven by current master to indicate beginning and
end of an access
REQ_L[3:0]
I
Request; indicates to arbiter that an external device requires use
of the bus
GNT_L[3:0]
T/S [2]
2. Tri-State Output.
Grant; indicates to device that bus access has been granted.
IRDY_L
STS
Initiator Ready; indicates the bus master’s ability to complete the
current data phase
TRDY_L
STS
Target Ready; indicates the selected device’s ability to complete
the current data phase
PERR_L
STS
Parity error; reports data parity errors
SERR_L
O/D
System Error; reports address parity errors, data parity errors on
special cycles, or any other catastrophic PCI errors
STOP_L
STS
Stop; indicates that the current target is requesting the master to
stop the current transaction
Interrupt Interface
Symbol
Volts
Type
Signal
Transitions
Aligned with:
Name and Function
SB_DRAIN
3.3 V
O
PCI_CLK
Store Buffer Drain. sampled at a 66 MHz PCI_CLK edge;
asserted after Interrupts, or by software, to cause outstanding
DMA writes to be ushed from buffers
SB_EMPTY[1:0]
I
Store Buffer Empty; sampled at 66 MHz PCI_CLK edge. asserted
when external APB PCI bus bridge indicates that all DMA writes
queued before the assertion of SB_DRAIN have left the bus
bridge;
INT_NUM[5:0]
I
Interrupt Number; sampled at 66 MHz PCI_CLK edge; encoded
interrupt request
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