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参数资料
| 型号： | SME1430LGA-480 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 480 MHz, RISC PROCESSOR, CBGA587 |
| 封装： | CERAMIC, LGA-587 |
| 文件页数： | 4/60页 |
| 文件大小： | 646K |
| 代理商： | SME1430LGA-480 |
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SME1430LGA-360
SME1430LGA-440
SME1430LGA-480
Highly Integrated 64-Bit RISC; L2-Cache, DRAM, PCI Interfaces
UltraSPARC-IIi CPU
May 1999
Sun Microsystems, Inc
TECHNICAL CAPABILITIES
.Newer compilers may improve SPECfp95 through use of software prefetch instructions.
The UltraSPARC-IIi CPU features superior performance of its integrated I/O, DRAM and UPA64S interface
s
Note that DRAM bandwidth is 1/3 to 1/4 greater than these numbers, since there is an initial DRAM read of
the data locations that are used for store operations.
SPEC Performance
Estimated Performance
Conditions
360 MHz CPU
SPECint95
15.1
using 50 ns DIMMs; 2-2-2 mode, 0.25 MB L2 cache
SPECfp95
18.0
440 MHz CPU
SPECint95
18.7
50 ns DIMMs; 2-2 mode, 2 MB L2 cache
SPECfp95
21.1
480 MHz CPU
SPECint95
20.2
50 ns DIMMs; 2-2 mode 2 MB L2 cache
SPECfp95
22.5
Memory Performance
Parameter
Specication (Estimated)
Unit
360 MHz CPU [1]
440 MHz CPU [2]
480 MHz CPU [3]
Maximum L2 cache read bandwidth
1.44
1.76
1.92
GB/s
Maximum L2 cache write bandwidth
1.44
1.76
1.92
GB/s
Maximum DRAM random read bandwidth
388
440
465
MB/s
Maximum DRAM random write bandwidth
388
440
465
MB/s
Maximum same page read bandwidth
480
586
639
MB/s
Memcopy, from DRAM to DRAM
351
410
436
MB/s
Memcopy, from DRAM to UPA64S bus
524
552
591
MB/s
FP Vector
Specication
Sustained Performance (Estimated)
Unit
360 MHz CPU [1]
1. 0.25 MB L2 cache in 2-2-2 mode;’ using 50 ns EDO DIMMs
440 MHz CPU [2]
2. 2.0 MB L2 cache in 2-2 mode; using 50 ns EDO DIMMs
480 MHz CPU [3]
3. 2.0 MB L2 cache in 2-2 mode; using 50 ns EDO DIMMs
STREAM Copy (compiled)
218
242
254
MB/s
STREAM Scale (compiled)
218
243
254
MB/s
STREAM Add (compiled)
248
274
286
MB/s
STREAM Triad (compiled)
248
274
286
MB/s
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