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参数资料
| 型号： | SME1430LGA-480 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 480 MHz, RISC PROCESSOR, CBGA587 |
| 封装： | CERAMIC, LGA-587 |
| 文件页数： | 18/60页 |
| 文件大小： | 646K |
| 代理商： | SME1430LGA-480 |
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Highly Integrated 64-Bit RISC; L2-Cache, DRAM, PCI Interfaces
UltraSPARC-IIi CPU
SME1430LGA-360
SME1430LGA-440
SME1430LGA-480
May 1999
Sun Microsystems, Inc
Direction of SCAN inputs and outputs through scan chains
UPA64S Interface
The UPA64S interface is a custom 64-bit slave bus interface for graphics or similar subsystems. Transfers to
and from the UPA64S interface are fully synchronous, since this interface receives a Low Voltage PECL
(LVPECL) clock that is aligned with the processor’s clock. The processor transfers data on clock edges that
correspond to the UPA64S clock edges. This interface runs at 1/4 of the processor clock rate, that is, up to 120
MHz.
Memory
The major features of the DRAM modules utilized in UltraSPARC-IIi memory are:
JEDEC and industry standard ECC pinout in a 168-pin, dual-in-line memory module (DIMM)
High performance CMOS silicon gate process
Single +3.3V
± 0.3 V power supply
All device pins are 3.3 V compatible
Low power, 9 mW standby; 1,800 mW active, typical
Refresh modes: CAS-BEFORE-RAS (CBR)
All inputs are buffered except RAS
2,048-cycle refresh distributed across 32 ms
Extended Data Out (EDO) access cycles
The UltraSPARC-IIi memory design can be built with JEDEC-standard, 168-pin DIMMs. The memory bus is
144 bits wide. The RAS and CAS signals that are provided support a maximum of eight 8–megabyte to
128-megabyte DIMMs. A mode that supports 11-bit column addresses for 16M X 4, 64 megabit DRAMs
allows a maximum of four 8–megabyte to 256-megabyte DIMMs. The memory bus width requires that the
DIMMs be populated in pairs at a time. Consequently the minimum memory conguration contains 16 mega-
bytes and the maximum memory conguration contains one gigabyte.
These DIMMs are available from many vendors. A composite specication was made considering typical
vendor specications. When the UltraSPARC-IIi CPU is programmed according to the UltraSPARC-IIi User’s
Manual for a particular frequency and DIMM loading combination, it generates signals that meet this com-
posite specication, if the electrical and topological motherboard layout requirements are met.
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