24
SME1430LGA-360
SME1430LGA-440
SME1430LGA-480
Highly Integrated 64-Bit RISC; L2-Cache, DRAM, PCI Interfaces
UltraSPARC-IIi CPU
May 1999
Sun Microsystems, Inc
Block Diagram of the Reference Platform
Figure 7. Overview of SME1430LGA Reference Platform
Transceivers
The transceivers consist of Texas Instruments SN74ALVC16268 bidirectional registered 12-bit-to-24-bit bus
exchangers with tri-state outputs.
The transceivers transfer data bidirectionally between the 72-bit UltraSPARC-IIi memory data bus, and the
144-bit DIMM memory data bus. The DIMMs are cycled in EDO mode according to the memory controller
programming.
The transceiver has bus-hold on data inputs, eliminating the need for external pullup resistors. It is available
in 56-pin Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) packages.
The ports connected to the DIMMs include the equivalent of 26
series resistors, to make external series ter-
mination resistors unnecessary on this side. Termination is not necessary on the CPU side with short bus
lengths and minimum loading.
The device provides synchronous data exchange between the two ports. Data is stored in the internal registers
on the low-to-high transition of the CLK input, provided that the appropriate CLKEN inputs are low. All con-
trol inputs, including the CLK inputs, are driven by the UltraSPARC-IIi CPU.
Reset/Interrupt/Clock Controller (RIC) Chip
The RIC Chip (SME2210) supports the system resets, system interrupts, system scan, and system clock control
functions. Its features include:
Support for resets from power supply, reset buttons, and scan
Concentration of the interrupts; it sends interrupt numbers to the UltraSPARC-IIi CPU
UPA64S
UltraSPARC-i
and L2 Cache
Advanced
PCI
Bridge
(APB)
RIC
10/100 Mb
Ethernet
Super I/O
10/100
XVER
MII
TP
8 KB
TOD/
NVRAM
Serial A/
B
Port
Kbd
Ctrlr.
EIDE
Con-
nector
Floppy
I MB
Boot
PROM
Transceivers
Memory DIMMs (8)
MEMADDR
+ Control
UPA64S
Address +
Control
MEMDATA
(64 + ECC)
Memory Data
(128 + 16 ECC)
PCI
32
/
PCI
32
/