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参数资料
| 型号： | SME1430LGA-480 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 480 MHz, RISC PROCESSOR, CBGA587 |
| 封装： | CERAMIC, LGA-587 |
| 文件页数： | 6/60页 |
| 文件大小： | 646K |
| 代理商： | SME1430LGA-480 |
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14
SME1430LGA-360
SME1430LGA-440
SME1430LGA-480
Highly Integrated 64-Bit RISC; L2-Cache, DRAM, PCI Interfaces
UltraSPARC-IIi CPU
May 1999
Sun Microsystems, Inc
SIGNAL DESCRIPTIONS [1] [2]
1. Unused inputs should be connected to the appropriate level.
2. Use approximately 10 k
resistors for pullups (unused) and 1 k for pulldowns. Never tie a pin directly to a to
a supply rail.
External Cache (L2-cache or E-cache) Interface
Symbol
Volts
Type
Signal
Transitions
Aligned with:
Name and Function
EDATA[63:0]
1.9 V
I/O
SRAM_CLK_A/B
L2-cache Data Bus; Connects
the UltraSPARC-IIi CPU to the
L2-cache data RAMs; clocked at 1/2 the processor clock rate
EDPAR[7:0]
I/O
L2-cache Data Parity; odd parity is driven or checked for all
EDATA transfers; MSB corresponds to the MS byte of EDATA;
clocked at 1/2 the processor clock rate
TDATA[15:0]
I/O
L2-cache Tag Data. Bits 15:14 carry the MEI I state; bits[13:0]
carry the physical address bits [31:18]; allows a minimum cache
size of 256k bytes; all TDATA bits are used, even when the
L2-cache is more than 256 kilobytes; clocked at 1/2 the processor
clock rate.
TPAR[1:0]
I/O
L2-cache Tag Parity; odd parity for TDATA[15:0]; TPAR[1] covers
TDATA[15:8]; TPAR[0] covers TDATA[7:0]; clocked at 1/2 the
processor clock rate
BYTEWE_L[7:0]
O
L2-cache Byte Write Enables; active low bit [0] controls
EDATA[63:56]; bit 7 controls EDATA[7:0]; clocked at 1/2 the
processor clock rate
ECAD[17:0]
O
L2-cache Data Address; corresponds to physical address [20:3];
allows a maximum 2 MB L2-cache; clocked at 1/2 the processor
clock rate
ECAT[14:0]
O
L2-cache Tag Address; corresponds to physical address [20:6];
allows a maximum 2 MB L2-cache, with 64-byte lines; clocked at
1/2 the processor clock rate
DSYN_WR_L
O
L2-cache Data Write Enable; active low; clocked at 1/2 the
processor clock rate
DOE_L
O
L2-cache Data Operation Enable; active low; asserted on all
SRAM operations; clocked at 1/2 the processor clock rate
TSYN_WR_L
O
L2-cache Tag Write Enable; active low; clocked at 1/2 the
processor clock rate
TOE_L
O
L2-cache Tag Operation Enable; active low; clocked at 1/2 the
processor clock rate
ECACHE_22_MODE
3.3 V
I
Not Aligned
Static (all
modes)
Selects L2-cache 22 (1-tie high) or 222 mode (0-tie low). (2 cycle
read pipeline, or 3 cycle read pipeline)
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