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参数资料
| 型号： | SME1430LGA-480 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 480 MHz, RISC PROCESSOR, CBGA587 |
| 封装： | CERAMIC, LGA-587 |
| 文件页数： | 14/60页 |
| 文件大小： | 646K |
| 代理商： | SME1430LGA-480 |
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Highly Integrated 64-Bit RISC; L2-Cache, DRAM, PCI Interfaces
UltraSPARC-IIi CPU
SME1430LGA-360
SME1430LGA-440
SME1430LGA-480
May 1999
Sun Microsystems, Inc
Memory and Transceiver Interface
Symbol
Volts
Type
Signal
Transitions
Aligned with:
Name and Function
MEM_WE_L
3.3 V
(All)
O
CLKA/B
Memory Write Enable; active low
MEM_CAS_L[1:0]
O
Memory Column Address Strobe; active low
MEM_RAST_L{3:0]
O
Memory Row Address Strobe Top; active low
MEM_RASB_L[3:0]
O
Memory Row Address Strobe Bottom, active low
MEM_DATA[71:0]
I/O
Memory Data; bits [71:64] are ECC bits
MEM_ADDR[12:0]
O
Memory Address, row and column (10 and 11 bit column
support)
XCVR_OEA_L
O
Transceiver Output Enable A; active low
XCVR_OEB_L
O
Transceiver Output Enable B; active low
XCVR_SEL_L
O
Transceiver Select; active low; picks high or low half of read data
XCVR_WR_CNTL[1:0]
O
Transceiver Write Control; controls lock enables on internal
registers
XCVR_RD_CNTL[1:0]
O
Transceiver Read Control; control clock enables on internal
registers
XCVR_CLK[2:0]
O
Transceiver Clock; all data and control signals are registered by
these clocks; multiple outputs to minimize loading effects of 6
transceivers
UPA64S Interface
Symbol
Volts
Type
Signal
Transitions
Aligned with:
Name and Function
S_REPLY[2:0]
3.3 V
O
UPA_CLK_POS/
UPA_CLK_NEG
S Reply; encoded command indicates arrival of write data on
MEM_DATA[63:0], or command to drive MEM_DATA[63:0] with
read data
P_REPLY[1:0]
I
P Reply; encoded command that indicates ability consumption of
prior write, or ability to provide read data
SYSADR[28:0]
I/O [1]
1. Not all of SYSADR[28:0] is bidirectional, since SYSADR[14:0] is I/O but SYSADR[28:15] is output only. SYSADR[14:0] is used as an input during
RAM_TEST.
System Address; sends 2 cycle address packet to UPA64S slave,
or provides internal state debug information
ADR_VLD
O
Address Valid; asserted during rst cycle of two cycle address
packet
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