- 您现在的位置：买卖IC网 > PDF目录98144 > ST72141K2B3/XXX (STMICROELECTRONICS) 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32 PDF资料下载
参数资料
| 型号： | ST72141K2B3/XXX |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32 |
| 封装： | 0.400 INCH, PLASTIC, SDIP-32 |
| 文件页数： | 10/133页 |
| 文件大小： | 2615K |
| 代理商： | ST72141K2B3/XXX |
第1页第2页第3页第4页第5页第6页第7页第8页第9页当前第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页
Obsolete
Product(s)
- Obsolete
ST72141K2
107/133
SERIAL PERIPHERAL INTERFACE (Cont’d)
STATUS REGISTER (SR)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7 = SPIF Serial Peripheral data transfer flag.
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the CR register. It is cleared by a soft-
ware sequence (an access to the SR register fol-
lowed by a read or write to the DR register).
0: Data transfer is in progress or has been ap-
proved by a clearing sequence.
1: Data transfer between the device and an exter-
nal device has been completed.
Note: While the SPIF bit is set, all writes to the DR
register are inhibited.
Bit 6 = WCOL Write Collision status.
This bit is set by hardware when a write to the DR
register is done during a transmit sequence. It is
cleared by a software sequence (see Figure 60).
0: No write collision occurred
1: A write collision has been detected
Bit 5 = Unused.
Bit 4 = MODF Mode Fault flag.
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 8.4.4.5
Master Mode Fault). An SPI interrupt can be gen-
erated if SPIE=1 in the CR register. This bit is
cleared by a software sequence (An access to the
SR register while MODF=1 followed by a write to
the CR register).
0: No master mode fault detected
1: A fault in master mode has been detected
Bits 3-0 = Unused.
DATA I/O REGISTER (DR)
Read/Write
Reset Value: Undefined
The DR register is used to transmit and receive
data on the serial bus. In the master device only a
write to this register will initiate transmission/re-
ception of another byte.
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
Warning:
A write to the DR register places data directly into
the shift register for transmission.
A read to the the DR register returns the value lo-
cated in the buffer and not the contents of the shift
register (See Figure 57 ).
70
SPIF
WCOL
-
MODF
-
70
D7
D6
D5
D4
D3
D2
D1
D0
相关PDF资料 |
PDF描述 |
|---|---|
| ST72311N4T6/XXX | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP64 |
| ST72311J2B6/XXX | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP42 |
| ST72311N2T3/XXX | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP64 |
| ST72321BAR7T6 | MICROCONTROLLER, QFP64 |
| ST72321BR7T3 | MICROCONTROLLER, QFP64 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ST72141K2B6 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-BIT MCU WITH ELECTRIC-MOTOR CONTROL, ADC, 16-BIT TIMERS, SPI INTERFACE |
| ST72141K2M1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-BIT MCU WITH ELECTRIC-MOTOR CONTROL, ADC, 16-BIT TIMERS, SPI INTERFACE |
| ST72141K2M3 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-BIT MCU WITH ELECTRIC-MOTOR CONTROL, ADC, 16-BIT TIMERS, SPI INTERFACE |
| ST72141K2M3/XXX | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Microcontroller |
| ST72141K2M6 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-BIT MCU WITH ELECTRIC-MOTOR CONTROL, ADC, 16-BIT TIMERS, SPI INTERFACE |
发布紧急采购，3分钟左右您将得到回复。