参数资料
型号: ST72141K2B3/XXX
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32
封装: 0.400 INCH, PLASTIC, SDIP-32
文件页数: 75/133页
文件大小: 2615K
代理商: ST72141K2B3/XXX
Obsolete
Product(s)
- Obsolete
Product(s)
ST72141K2
46/133
MOTOR CONTROLLER (Cont’d)
Sensorless Mode
This mode is used to detect BEMF zero crossing
and end of demagnetization events.
The analog phase multiplexer connects the non-
excited motor winding to an analog 100mV hyster-
esis comparator referred to a selectable reference
voltage.
The VR[1:0] bits in the MCRB register select the
reference voltage from four internal values de-
pending on the noise level and the application volt-
age supply.
BEMF detections are performed during the meas-
urement window, when the excited windings are
free-wheeling through the low side switches and
diodes. At this stage the common star connection
voltage is near to ground voltage (instead of VDD/2
when the excited windings are powered) and the
complete BEMF voltage is present on the non-ex-
cited winding terminal, referred to the ground ter-
minal.
The zero crossing sampling frequency is then de-
fined, in current mode, by the measurement win-
dow generator frequency (SA[3:0] bits in the
MPRSR register) or, in voltage mode, by the 16-bit
Timer PWM frequency and duty cycle.
During a short period after a phase commutation
(C event), the winding is no longer excited but
needs a demagnetisation phase during which the
BEMF cannot be read. A demagnetization current
goes through the free-wheeling diodes and the
winding voltage is stuck at the high voltage or to
the ground terminal. For this reason an “end of de-
magnetization event” D must be detected on the
winding before the detector can sense a BEMF
zero crossing.
For the end-of-demagnetization detection, no spe-
cial PWM configuration is needed, the comparator
sensing is done at a fixed 800kHz sampling fre-
quency.
So, the three events: C (commutation), D (demag-
netization) and Z (BEMF zero crossing) must al-
ways occur in this order.
The comparator output is processed by a detector
that automatically recognizes the D or Z event, de-
pending on the CPB or ZVD edge and level config-
uration bits as described in Table 13.
A 20
s filter after a C event disables a D event if
spurious spikes occur.
Another 20
s filter after a D event disables a Z
event if spurious spikes occur.
Table 13. ZVD and CPB Edge Selection Bits
ZVD bit
CPB bit
Event generation vs input data sampled
00
01
10
11
Note: The ZVD bit is located in the MPAR register, the CPB bit is in the MCRB register.
CDH
Z
20-s filter
CDH
Z
20-s filter
CDH
Z
20-s filter
CDH
Z
20-s filter
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