Obsolete
Product(s)
- Obsolete
Product(s)
ST72141K2
120/133
10.5 I/O PORT CHARACTERISTICS
Recommended operating conditions
with TA=-40 to +125
oC and 4.5V<V
DD-VSS<5.5V unless otherwise specified.
Notes:
1) Unless otherwise specified, typical data is based on TA=25°C and VDD-VSS=5V. This data is provided only as design
guidelines and is not tested.
2) Data based on design simulations and/or technology characteristics, not tested in production.
3) Hysteresis voltage between Schmitt trigger switching levels. Based on characterisation results, not tested.
4) Data based on characterization results, not tested in production.
5) Positive injection (IINJ+)
The IINJ+ is performed through protection diodes insulated from the substrate of the die.
The true open-drain pins do not accept positive injection. In this case the maximum voltage rating must be respected.
6) ADC accuracy reduced by negative injection (IINJ- )
The IINJ- is performed through protection diodes NOT INSULATED from the substrate of the die. The drawback is a small
leakage (a few
μA) induced inside the die when a negative injection is performed. This leakage is tolerated by the digital
structure, but it acts on the analog line depending on the impedance versus a leakage current of a few
μA (if the MCU
has an AD converter). The effect depends on the pin which is submitted to the injection. Of course, external digital signals
applied to the component must have a maximum impedance close to 50K
Ω.
Location of the negative current injection:
- Pins with analog input capability are the most sensitive. IINJ- maximum is 0.8 mA (assuming that the impedance of the
analog voltage is lower than 25K
Ω)
- Pure digital pins can tolerate 1.6mA. In addition, the best choice is to inject the current as far as possible from the analog
input pins.
7) When several inputs are submitted to a current injection, the maximum IINJ is the sum of the positive (or negative) cur-
rents (instantaneous values). These results are based on characterisation with IINJ maximum current injection on four I/
O port pins of the device.
8) To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
I/O PORT PINS
Symbol
Parameter
Conditions
Min
Typ 1)
Max
Unit
VIL
Input low level voltage 2)
0.3xVDD
V
VIH
Input high level voltage 2)
0.7xVDD
VHYS
Schmitt trigger voltage hysteresis 3)
400
mV
VOL
Output low level voltage
for standard I/O port pins
I=-5mA
1.3
V
I=-2mA
0.5
Output low level voltage
for high sink I/O port pins
I=-20mA
1.3
I=-8mA
0.5
VOH
Output high level voltage
I=-5mA
VDD-2.0
I=-2mA
VDD-0.8
RPU
Pull-up equivalent resistor
VIN > VIH
VIN < VIL
20
50
40
120
80
240
k
Ω
IL
Input leakage current
VSS<VPIN<VDD
1
μA
ISV
Static current consumption 2)
Floating input mode
200
IPINJ
Single pin injected current
Positive 5): VEXT>VDD
5
mA
Negative 6): VEXT<VSS
-5
IINJ
Total injected current 7)
(sum of all I/O and control pins)
Positive: VEXT>VDD
20
Negative: VEXT<VSS
20
tOHL
Output high to low level fall time
Cl=50pF
14.8 4)
25
45.6 4)
ns
tOLH
Output low to high rise time
14.4 4)
25
45.9 4)
tITEXT
External interrupt pulse time 8)
1tCPU