参数资料
型号: ST72F651AR6T1
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, MICROCONTROLLER, PQFP64
封装: 10 X 10 MM, ROHS COMPLIANT, TQFP-64
文件页数: 120/161页
文件大小: 2656K
代理商: ST72F651AR6T1
ST72651AR6
61/161
Doc ID 7215 Rev 4
11.3 USB INTERFACE (USB)
11.3.1 Introduction
The USB Interface implements a full-speed func-
tion interface between the USB and the ST7 mi-
crocontroller. It is a highly integrated circuit which
includes the transceiver, 3.3 voltage regulator, SIE
and USB Data Buffer interface. No external com-
ponents are needed apart from the external pull-
up on USBDP for full speed recognition by the
USB host.
11.3.2 Main Features
USB Specification Version 2.0 Compliant
Supports Full-Speed USB Protocol
Five Endpoints (including default endpoint)
CRC
generation/checking,
NRZI
encoding/
decoding and bit-stuffing
USB Suspend/Resume operations
Special Data transfer mode with USB Data
Buffer Memory (2 x 512 bytes for upload or
download) to DTC
On-Chip 3.3V Regulator
On-Chip USB Transceiver
11.3.3 Functional Description
The block diagram in Figure 36, gives an overview
of the USB interface hardware.
For general information on the USB, refer to the
“Universal Serial Bus Specifications” document
available at http//:www.usb.org.
Serial Interface Engine
The SIE (Serial Interface Engine) interfaces with
the USB, via the transceiver.
The SIE processes tokens, handles data transmis-
sion/reception, and handshaking as required by
the USB standard. It also performs frame format-
ting, including CRC generation and checking.
Endpoints
The Endpoint registers indicate if the microcon-
troller is ready to transmit/receive, and how many
bytes need to be transmitted.
Data Transfer to/from USB Data Buffer Memory
When a token for a valid Endpoint is recognized by
the USB interface, the related data transfer takes
place to/from the USB data buffer. In normal con-
figuration (MOD[1:0] bits=00 in the CTLR register),
at the end of the transaction, an interrupt is gener-
ated.
Interrupts
By reading the Interrupt Status register, applica-
tion software can know which USB event has oc-
curred.
Figure 36. USB Block Diagram
CPU
Transceiver
3.3V
Voltage
Regulator
SIE
ENDPOINT
BUFFER
USB
Address,
and interrupts
USBDM
USBDP
USBVCC
48 MHz
REGISTERS
data busses
USBGND
BUFFER
USB
DATA
INTERFACE
1
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