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参数资料
| 型号： | ST72F651AR6T1 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, MICROCONTROLLER, PQFP64 |
| 封装： | 10 X 10 MM, ROHS COMPLIANT, TQFP-64 |
| 文件页数： | 15/161页 |
| 文件大小： | 2656K |
| 代理商： | ST72F651AR6T1 |
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ST72651AR6
111/161
Doc ID 7215 Rev 4
IC SINGLE MASTER BUS INTERFACE (Cont’d)
I2C STATUS REGISTER 1 (SR1)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7 = EVF Event flag.
This bit is set by hardware as soon as an event oc-
curs. It is cleared by software reading SR2 register
in case of error event or as described in Figure 64.
It is also cleared by hardware when the interface is
disabled (PE=0).
0: No event
1: One of the following events has occurred:
– BTF=1 (Byte received or transmitted)
– SB=1 (Start condition generated)
– AF=1 (No acknowledge received after byte
transmission if ACK=1)
– Address byte successfully transmitted.
Bit 6 = Reserved. Forced to 0 by hardware.
Bit 5 = TRA Transmitter/Receiver.
When BTF is set, TRA=1 if a data byte has been
transmitted. It is cleared automatically when BTF
is cleared. It is also cleared by hardware when the
interface is disabled (PE=0).
0: Data byte received (if BTF=1)
1: Data byte transmitted
Bit 4 = Reserved. Forced to 0 by hardware.
Bit 3 = BTF Byte transfer finished.
This bit is set by hardware as soon as a byte is cor-
rectly received or transmitted with interrupt gener-
ation if ITE=1. It is cleared by software reading
SR1 register followed by a read or write of DR reg-
ister. It is also cleared by hardware when the inter-
face is disabled (PE=0).
– Following a byte transmission, this bit is set after
reception of the acknowledge clock pulse. In
case an address byte is sent, this bit is set only
after the EV2 event (See Figure 64). BTF is
cleared by reading SR1 register followed by writ-
ing the next byte in DR register.
– Following a byte reception, this bit is set after
transmission of the acknowledge clock pulse if
ACK=1. BTF is cleared by reading SR1 register
followed by reading the byte from DR register.
The SCL line is held low while BTF=1.
0: Byte transfer not done
1: Byte transfer succeeded
Bit 2 = Reserved. Forced to 0 by hardware.
Bit 1 = M/IDL Master/Idle.
This bit is set by hardware as soon as the interface
is in Master mode (writing START=1). It is cleared
by hardware after generating a Stop condition on
the bus. It is also cleared when the interface is dis-
abled (PE=0).
0: Idle mode
1: Master mode
Bit 0 = SB Start bit generated.
This bit is set by hardware as soon as the Start
condition
is
generated
(following
a
write
START=1). An interrupt is generated if ITE=1. It is
cleared by software reading SR1 register followed
by writing the address byte in DR register. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
0: No Start condition
1: Start condition generated
70
EVF
0
TRA
0
BTF
0
M/IDL
SB
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相关代理商/技术参数 |
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| ST72F651AR6T1E | 功能描述:8位微控制器 -MCU Flash 32K USB/DTC/I2 RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
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