参数资料
型号: ST72F651AR6T1
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, MICROCONTROLLER, PQFP64
封装: 10 X 10 MM, ROHS COMPLIANT, TQFP-64
文件页数: 41/161页
文件大小: 2656K
代理商: ST72F651AR6T1
ST72651AR6
135/161
Doc ID 7215 Rev 4
13.8 I/O PORT PIN CHARACTERISTICS
13.8.1 General Characteristics
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
3. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure ). Data based on design simulation and/or technology
characteristics, not tested in production.
4. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics de-
scribed in Figure 77). This data is based on characterization results, tested in production at VDD=5V.
5. Data based on characterization results, not tested in production.
6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
Figure 75Two typical Applications with unused I/O Pin
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
Input low level voltage
VDD = 5.0V
Vss
0.3xVDD
V
VIH
Input high level voltage
VDD = 5.0V
0.7xVDD
VDD
Vhys
Schmitt trigger voltage hysteresis 2)
400
mV
IL
Input leakage current
VSSVINVDD
±1
μA
IS
Static current consumption 3)
Floating input mode
200
RPU
Weak pull-up equivalent resistor 4)
VIN=VSS
VDD=5V
70
100
130
k
Ω
VDD=3V
130
200
260
CIO
I/O pin capacitance 5)
5pF
tf(IO)out
Output high to low level fall time 5)
CL=50pF
Between 10% and 90%
25
ns
tr(IO)out
Output low to high level rise time 5)
25
tw(IT)in
External interrupt pulse time 6)
1tCPU
10k
Ω
UNUSED I/O PORT
ST72XXX
10k
Ω
UNUSED I/O PORT
ST72XXX
VDD
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