- 您现在的位置：买卖IC网 > PDF目录195890 > ST72T734J6B1 (意法半导体) 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C PDF资料下载
参数资料
| 型号： | ST72T734J6B1 |
| 厂商： | 意法半导体 |
| 元件分类： | ADC |
| 英文描述： | 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C |
| 中文描述： | 8位USB单片机的显示器，高达60K章检察官办公室，每1000内存，模数转换器，定时器，同步，材质单元，脉宽调制/的BRM，的H / W DDC的 |
| 文件页数： | 103/144页 |
| 文件大小： | 1280K |
| 代理商： | ST72T734J6B1 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页当前第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页
ST72774/ST727754/ST72734
61/144
SYNC PROCESSOR (SYNC) (Cont’d)
4.4.6 Input Processing
4.4.6.1 Detecting Signal Presence
The Sync Processor provides two ways of
checking input signal presence, by directly polling
the LATR Latch Register or using the Timer
interrupts.
Polling check
Use the Latch Register (LATR), to detect the
presence
of
HSYNCI,
VSYNCI,
CSYNCI,
HFBACK and VFBACK signals. These latched bits
are set when the falling edge of the corresponding
signal is detected. They are cleared by software.
Interrupts check
Due to the fact that VSYNCI is connected to Timer
Input Capture 1 and HSYNCI or CSYNCI is
connected to Timer Input Capture 2, the Timer
interrupts can be used to detect the presence of
input signals. Refer to the 16-bit Timer chapter for
the description of the Timer registers.
To use the interrupt method:
– Select Input Capture1 edge detection:
IEDG1 bit in the Timer CR1 register
– Select Input Capture 2 edge detection (must be
falling edge):
IEDG2 bit = 0 in the Timer CR2 register
– Enable Timer Input Capture interrupts:
ICIE bit in the Timer CR1 register.
– Select the Hsync and Vsync input signals:
HVSEL bit in the POLR register
– Enable the prescaler for HSYNCI or CSYNCI
signal:
PSCD bit in the CCR register.
– Select the normal mode:
LCV1/LCV0 bits in the CCR register.
Perform any of the following:
– Check for VSYNCI presence by monitoring inter-
rupt requests from Timer ICAP1. When VSYNCI
is detected then either detect the VSYNCI polar-
ity or check for HSYNCI presence.
– Check for HSYNCI presence by monitoring inter-
rupt requests from Timer ICAP2. On detecting
HSYNCI, either detect its polarity or check if the-
composite sync on HSYNCI pin is detected or
check for CSYNCI presence.
– Check for CSYNCI presence by monitoring inter-
rupt requests from Timer ICAP2.
4.4.6.2 Measuring Sync Period
To measure the sync period, the Sync processor
block uses the Timer Input Capture interrupts:
– ICAP1 connected to VSYNCI signal
– ICAP2 connected to HSYNCI/CSYNCI signal
with a 256 prescaler
Calculating
the
difference
between
two
subsequent Input Captures (16-bit value) gives the
period for 256xPH (horizontal period) and PV
(vertical period).
The period accuracy is one timer clock (500ns at 2
MHz), so that the tolerance is 500ns for PH and
256 * PH (PH accuracy =1.95ns).
Notes:
1) In case of composite sync, the HSYNCI period
measurement can be synchronized on the
VSYNCI pulse by setting and resetting the
prescaler PSCD bit in the CCR register (for this
function, the ICAP2 detection must be selected
as falling edge).
This avoids errors in the period measurement
due to the Vsync pulse.
2) The Timer Interrupt request should be masked
during a write access to any of the Sync
processor control registers.
Important Note:
Since the recognition of the video mode relies
on the accuracy of the measurements, it is
highly recommended to implement a counter-
style
algorithm
which
performs
several
consecutive measurements before switching
between modes.
The purpose of this algorithm is to filter out any
glitches occurring on the video signals.
相关PDF资料 |
PDF描述 |
|---|---|
| ST72T754J9B1 | 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C |
| ST72T754S9T1 | 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C |
| ST733C08LFK2 | 1900 A, 800 V, SCR, TO-200AC |
| ST733C08LFK1L | 1900 A, 800 V, SCR, TO-200AC |
| ST733C04LEK1 | 1900 A, 400 V, SCR, TO-200AC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ST72T754J9B1 | 制造商:STMicroelectronics 功能描述: |
| ST72T774J9B1 | 制造商:STMicroelectronics 功能描述: |
| ST72T774S9T1 | 制造商:STMicroelectronics 功能描述:ST72T774S9T1 - Trays |
| ST730 | 制造商:IRF 制造商全称:International Rectifier 功能描述:PHASE CONTROL THYRISTORS Hockey Puk Version |
| ST7-30 | 制造商:SUPERWORLD 制造商全称:Superworld Electronics 功能描述:POWER TRANSFORMER |
发布紧急采购，3分钟左右您将得到回复。