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参数资料
| 型号： | ST72T734J6B1 |
| 厂商： | 意法半导体 |
| 元件分类： | ADC |
| 英文描述： | 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C |
| 中文描述： | 8位USB单片机的显示器，高达60K章检察官办公室，每1000内存，模数转换器，定时器，同步，材质单元，脉宽调制/的BRM，的H / W DDC的 |
| 文件页数： | 129/144页 |
| 文件大小： | 1280K |
| 代理商： | ST72T734J6B1 |
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USB INTERFACE (Cont’d)
4.6.5 Programming Considerations
In the following, the interaction between the USB
interface and the application program is described.
Apart from system reset, action is always initiated
by the USB interface, driven by one of the USB
events
associated
with
the
Interrupt
Status
Register (ISTR) bits.
4.6.5.1 Initializing the Registers
At system reset, the software must initialize all
registers to enable the USB interface to properly
generate interrupts and DMA requests.
1. Initialize the DMAR, IDR, and IMR registers
(choice of enabled interrupts, address of DMA
buffers). Refer the paragraph titled initializing
the DMA Buffers.
2. Initialize the EP0RA and EP0RB registers to
enable accesses to address 0 and endpoint 0
to support USB enumeration. Refer to the para-
graph titled Endpoint Initialization.
3. When addresses are received through this
channel, update the content of the DADDR.
4. If needed, write the endpoint numbers in the EA
fields in the EP1RB and EP2RB register.
4.6.5.2 Initializing DMA buffers
The DMA buffers are a contiguous zone of
memory whose maximum size is 48 bytes. They
can be placed anywhere in the memory space,
typically in RAM, to enable the reception of
messages. The 10 most significant bits of the start
of this memory area are specified by bits DA15-
DA6 in registers DMAR and IDR, the remaining
bits are 0. The memory map is shown in Figure 51.
Each buffer is filled starting from the bottom (last 3
address bits=000) up.
4.6.5.3 Endpoint Initialization
To be ready to receive:
Set STAT_RX to VALID (11b) in EP0RB to enable
reception.
To be ready to transmit:
1. Write the data in the DMA transmit buffer.
2. In register EPnRA, specify the number of bytes
to be transmitted in the TBC field
3. Enable the endpoint by setting the STAT_TX
bits to VALID (11b) in EPnRA.
Note: Once transmission and/or reception are enabled,
registers EPnRA and/or EPnRB (respectively) must
not be modified by software, as the hardware can
change their value on the fly.
When the operation is completed, they can be
accessed again to enable a new operation.
4.6.5.4 Interrupt Handling
Start of Frame (SOF)
The interrupt service routine must monitor the SOF
events and measure the interval between each
SOF event. If 3ms pass without a SOF event, the
software should set the USB interface to suspend
mode.
USB Reset (RESET)
When this event occurs, the DADDR register is
reset, and communication is disabled in all
endpoint registers (the USB interface will not
respond to any packet). Software is responsible for
reenabling endpoint 0 within 10 ms of the end of
reset. To do this you set the STAT_RX bits in the
EP0RB register to VALID.
End Suspend (ESUSP)
The CPU is alerted by activity on the USB, which
causes an ESUSP interrupt.
Correct Transfer (CTR)
1. When this event occurs, the hardware automat-
ically sets the STAT_TX or STAT_RX to NAK.
Note: Every valid endpoint is NAKed until software clears
the CTR bit in the ISTR register, independently of
the endpoint number addressed by the transfer
which generated the CTR interrupt.
Note: If the event triggering the CTR interrupt is a SETUP
transaction, both STAT_TX and STAT_RX are set
to NAK.
2. Read the PIDR to obtain the token and the IDR
to get the endpoint number related to the last
transfer.
Note: When a CTR interrupt occurs, the TP3-TP2 bits in
the PIDR register and EP1-EP0 bits in the IDR reg-
ister stay unchanged until the CTR bit in the ISTR
register is cleared.
3. Clear the CTR bit in the ISTR register.
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