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| 型号： | ST72T734J6B1 |
| 厂商： | 意法半导体 |
| 元件分类： | ADC |
| 英文描述： | 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C |
| 中文描述： | 8位USB单片机的显示器，高达60K章检察官办公室，每1000内存，模数转换器，定时器，同步，材质单元，脉宽调制/的BRM，的H / W DDC的 |
| 文件页数： | 136/144页 |
| 文件大小： | 1280K |
| 代理商： | ST72T734J6B1 |
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IC SINGLE MASTER BUS INTERFACE (Cont’d)
4.7.5 Register Description
I2C CONTROL REGISTER (CR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7:6 = Reserved. Forced to 0 by hardware.
Bit 5 = PE
Peripheral enable.
This bit is set and cleared by software.
0: Peripheral disabled
1: Master capability
Note: When PE=0, all the bits of the CR register and the
SR register except the Stop bit are reset. All outputs
are released while PE=0
Note: When PE=1, the corresponding I/O pins are select-
ed by hardware as alternate functions.
Note: To enable the I2C interface, write the CR register
TWICE with PE=1 as the first write only activates
the interface (only PE is set).
Bit 4 = Reserved. Forced to 0 by hardware.
Bit 3 = START
Generation of a Start condition.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disabled
(PE=0) or when the Start condition is sent (with
interrupt generation if ITE=1).
In master mode:
0: No start generation
1: Repeated start generation
In idle mode:
0: No start generation
1: Start generation when the bus is free
Bit 2 = ACK
Acknowledge enable.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disabled
(PE=0).
0: No acknowledge returned
1: Acknowledge returned after a data byte is re-
ceived
Bit 1 = STOP
Generation of a Stop condition.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disabled
(PE=0) or when the Stop condition is sent.
In Master mode only:
0: No stop generation
1: Stop generation after the current byte transfer
or after the current Start condition is sent.
Bit 0 = ITE
Interrupt enable.
This bit is set and cleared by software and cleared
by hardware when the interface is disabled
(PE=0).
0: Interrupts disabled
1: Interrupts enabled
Refer to Figure 55 for the relationship between the
events and the interrupt.
SCL is held low when the SB or BTF flags or an
EV2 event (See Figure 54) is detected.
70
0
PE
0
START
ACK
STOP
ITE
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