参数资料
型号: ST72T734J6B1
厂商: 意法半导体
元件分类: ADC
英文描述: 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C
中文描述: 8位USB单片机的显示器,高达60K章检察官办公室,每1000内存,模数转换器,定时器,同步,材质单元,脉宽调制/的BRM,的H / W DDC的
文件页数: 116/144页
文件大小: 1280K
代理商: ST72T734J6B1
ST72774/ST727754/ST72734
73/144
SYNC PROCESSOR (SYNC) (Cont’d)
ENABLE REGISTER (ENR)
Read/Write
Reset Value: 1100 0011 (C3h)
Bit 7 = SYNOP
HSYNCO, VSYNCO outputs
enable
0: Enabled
1: Disabled
Bit 6 = CLMPEN
Clamping or Moire output ena-
ble
0: Clamping or Moire output (function of BP0,
BP1) enabled
1: Clamping or Moire output disabled
Bit 5 = BLKEN
Blanking Output
0: Disabled
1: Enabled
Bit 4 = HVGEN
Sync Generation function
0: Analyzer/Corrector Mode
1: Generation of HSYNCO and VSYNCO free-
running frequencies
Bit 3 = 2FHEN
VSYNCO Extension
VSYNCO is forced high when detecting pre- and
post-equalization pulses. It is valid when the sync
generator and analyzer are disabled (HVGEN = 0,
HACQ = 0, VACQ = 0). Refer to the procedure in
Section 4.4.9 Corrector Mode.
0: Disabled
1: Enabled
Bit 2 = HINH
HSYNCO Blanking
HSYNCO
is
blanked
during
the
extracted
VSYNCO pulse.
0: Enabled
1: Disabled
Bit 1 = HSIN1 (read only)
Returns the HSYNCI1 pin level
Bit 0 = VSIN1 (read only)
Returns the VSYNCI1 pin level
Table 20. Summary of the Main Sync Processor Modes
70
SYNOP CLMPEN BLKEN HVGEN 2FHEN HINH HSIN1 VSIN1
Sync Processor Mode
SYNOP
HVSEL
HVGEN
HACQ
VACQ
DSUB Selected as Inputs
(HSYNCI1/VSYNCI1)
---
1
---
BNC Selected as Inputs
(HSYNCI2/VSYNCI2)
---
0
---
Don’t drive the monitor
with any Sync signals
1
---
Generate Sync Signals
to drive the Monitor hardware
0
---
1
0
Use the Sync Processor
to drive the monitor hardware
by incoming Sync signals
0
---
0
---
Analyse the number of Scan Lines
during one vertical frame
---
--
0
---
1
Analyse the HSYNC delay
between two pulses
---
0
1
---
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