- 您现在的位置：买卖IC网 > PDF目录195890 > ST72T734J6B1 (意法半导体) 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C PDF资料下载
参数资料
| 型号： | ST72T734J6B1 |
| 厂商： | 意法半导体 |
| 元件分类： | ADC |
| 英文描述： | 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C |
| 中文描述： | 8位USB单片机的显示器，高达60K章检察官办公室，每1000内存，模数转换器，定时器，同步，材质单元，脉宽调制/的BRM，的H / W DDC的 |
| 文件页数： | 104/144页 |
| 文件大小： | 1280K |
| 代理商： | ST72T734J6B1 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页当前第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页
ST72774/ST727754/ST72734
62/144
SYNC PROCESSOR (SYNC) (Cont’d)
4.4.6.3 Detecting Signal Polarity
The Sync Processor provides two ways for
checking input signal polarity by polling the latches
or using the 5-bit up/down counter.
Polling check
– HSYNCI polarity detection:
UPLAT/DWNLAT bits in LATR register
These bits are directly connected to the 5-bit
Up/Down counter.
UPLAT=1/ DOWNLAT=0 HSYNCI polarity<0
UPLAT=0/ DOWNLAT=1 HSYNCI polarity>0
– VSYNCI Polarity Detection
– VPOL bit (VSYNCO polarity) in POLR and
– VOP bit (VSYNCO polarity control) in MCR
The delay between VSYNCI polarity changes
and the VPOL bit typically toggles within 4
msecs. The polarity detector includes an
integrator to filter possible incoming VSYNCI
glitches.
5-bit Up/Down Counter Check
for HSYNCI Polarity
This method involves the internal 5-bit up/down
counter.
The counter value (CV4-CV0 bits) is updated with
the 5-bit counter value at every detected edge on
the signal monitored.
It is incremented when the signal is high, otherwise
it is decremented.
– Start the detection phase:
Initialize the 5-bit counter: write '00000' in the
CCR register (CV4-CV0 bits).
Select normal mode on falling edge:
LCV1/LCV0 = 0 in the CCR register.
– Software checks the counter value (CV4-CV0)
after an interrupt (with the signal internally con-
nected or ICAP2) or by polling (timeout 150s).
Positive polarity: The counter value < 1Fh.
Negative polarity: The counter value =1Fh on
the falling edge.
In case of a composite incoming signal, the
software just has to check that the VSYNCO
period and polarity are stable.
4.4.6.4 Extracting VSYNCO from CSYNCI
In case of composite sync, the Vertical sync output
signal is extracted with the 5-bit up/down counter.
Initially,
the
width
of
an
Horizontal
Sync
component pulse is automatically determined by
hardware which defines a threshold for the 5-bit
counter with a possible user-defined tolerance.
The circuit then monitors for any incoming period
greater than this previously captured value. This is
then processed as the VSYNCO signal.
To use the Vsync extractor, the following steps are
necessary:
– Detection of a composite sync signal:
When the UPLAT and DOWNLAT bits in LATR
register are set, a composite sync signal or a
HSYNCI polarity change is detected.
If these bits are stable during two subsequent
ICAP2 interrupt, the composite sync signal is
stable.
– Defining a threshold:
Select the normal mode (LCV1/LCV0=0 in the
CCR register).
Initialize the counter capture CV4-CV0 to 0.
This automatically measures the HSYNCI pulse
width. It defines a threshold in the CV4-CV0 bits
used by the 5-bit up/down counter.
It also allows to check the HSYNCI polarity
(refer to the “5-bit Up/Down Counter Check”
paragraph.
If a user-defined tolerance is to be added, then
an updated value should be written in the CCR
register (CV4-CV0 bits).
In a composite sync signal, Hsync and Vsync
always have the same polarity.
– Starting the VSYNCO hardware extraction
mode:
According to the Composite sync polarity, select
the extraction mode (LCV1/LCV0 in CCR
register) and rewrite the counter if necessary.
Negative polarity: minimum threshold (00h)
Positive polarity: maximum threshold (1Fh)
Note:
The
extracted
VSYNCO
signal
always
has
negative polarity.
相关PDF资料 |
PDF描述 |
|---|---|
| ST72T754J9B1 | 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C |
| ST72T754S9T1 | 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C |
| ST733C08LFK2 | 1900 A, 800 V, SCR, TO-200AC |
| ST733C08LFK1L | 1900 A, 800 V, SCR, TO-200AC |
| ST733C04LEK1 | 1900 A, 400 V, SCR, TO-200AC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ST72T754J9B1 | 制造商:STMicroelectronics 功能描述: |
| ST72T774J9B1 | 制造商:STMicroelectronics 功能描述: |
| ST72T774S9T1 | 制造商:STMicroelectronics 功能描述:ST72T774S9T1 - Trays |
| ST730 | 制造商:IRF 制造商全称:International Rectifier 功能描述:PHASE CONTROL THYRISTORS Hockey Puk Version |
| ST7-30 | 制造商:SUPERWORLD 制造商全称:Superworld Electronics 功能描述:POWER TRANSFORMER |
发布紧急采购，3分钟左右您将得到回复。