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参数资料
| 型号： | ST72T734J6B1 |
| 厂商： | 意法半导体 |
| 元件分类： | ADC |
| 英文描述： | 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C |
| 中文描述： | 8位USB单片机的显示器，高达60K章检察官办公室，每1000内存，模数转换器，定时器，同步，材质单元，脉宽调制/的BRM，的H / W DDC的 |
| 文件页数： | 53/144页 |
| 文件大小： | 1280K |
| 代理商： | ST72T734J6B1 |
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ST72774/ST727754/ST72734
16/144
CPU REGISTERS (Cont’d)
CONDITION CODE REGISTER (CC)
Read/Write
Reset Value: 111x1xxx
The 8-bit Condition Code register contains the
interrupt mask and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP
instructions.
These bits can be individually tested and/or
controlled by specific instructions.
Bit 4 = H
Half carry.
This bit is set by hardware when a carry occurs
between bits 3 and 4 of the ALU during an ADD or
ADC instruction. It is reset by hardware during the
same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH
instruction. The H bit is useful in BCD arithmetic
subroutines.
Bit 3 = I
Interrupt mask.
This bit is set by hardware when entering in
interrupt or by software to disable all interrupts
except the TRAP software interrupt. This bit is
cleared by software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET
instructions and is tested by the JRM and JRNM
instructions.
Note: Interrupts requested while I is set are
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptable
because the I bit is set by hardware when you
enter it and reset by the IRET instruction at the end
of the interrupt routine. If the I bit is cleared by
software in the interrupt routine, pending interrupts
are serviced regardless of the priority level of the
current interrupt routine.
Bit 2 = N
Negative.
This bit is set and cleared by hardware. It is
representative of the result sign of the last
arithmetic, logical or data manipulation. It is a copy
of the 7th bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL
instructions.
Bit 1 = Z
Zero.
This bit is set and cleared by hardware. This bit
indicates that the result of the last arithmetic,
logical or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 0 = C
Carry/borrow.
This bit is set and cleared by hardware and
software. It indicates an overflow or an underflow
has occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
70
11
1
H
I
N
Z
C
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