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参数资料
| 型号： | ST7FSCR1E4U1 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, QCC64 |
| 封装： | QFN-64 |
| 文件页数： | 21/101页 |
| 文件大小： | 4506K |
| 代理商： | ST7FSCR1E4U1 |
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ST7SCR1E4 ST7SCR1R4
26/101
INTERRUPTS (Cont’d)
Servicing Pending Interrupts
As several interrupts can be pending at the same
time, the interrupt to be taken into account is deter-
mined by the following two-step process:
– the highest software priority interrupt is serviced,
– if several interrupts have the same software pri-
ority then the interrupt with the highest hardware
priority is serviced first.
Figure 18 describes this decision process.
Figure 18. Priority Decision Process
When an interrupt request is not serviced immedi-
ately, it is latched and then processed when its
software priority combined with the hardware pri-
ority becomes the highest one.
Note 1: The hardware priority is exclusive while
the software one is not. This allows the previous
process to succeed with only one interrupt.
Note 2: RESET, TRAP and TLI can be considered
as having the highest software priority in the deci-
sion process.
Different Interrupt Vector Sources
Two interrupt source types are managed by the
CPU interrupt controller: the non-maskable type
(RESET, TLI, TRAP) and the maskable type (ex-
ternal or from internal peripherals).
Non-Maskable Sources
These sources are processed regardless of the
state of the I1 and I0 bits of the CC register (see
Figure 17). After stacking the PC, X, A and CC
registers (except for RESET), the corresponding
vector is loaded in the PC register and the I1 and
I0 bits of the CC are set to disable interrupts (level
3). These sources allow the processor to exit
HALT mode.
■ TLI (Top Level Hardware Interrupt)
This hardware interrupt occurs when a specific
edge is detected on the dedicated TLI pin.
Caution: A TRAP instruction must not be used in a
TLI service routine.
■ TRAP (Non Maskable Software Interrupt)
This software interrupt is serviced when the TRAP
instruction is executed. It will be serviced accord-
ing to the flowchart in Figure 17 as a TLI.
Caution: TRAP can be interrupted by a TLI.
■ RESET
The RESET source has the highest priority in the
CPU. This means that the first current routine has
the highest software priority (level 3) and the high-
est hardware priority.
See the RESET chapter for more details.
Maskable Sources
Maskable interrupt vector sources can be serviced
if the corresponding interrupt is enabled and if its
own interrupt software priority (in ISPRx registers)
is higher than the one currently being serviced (I1
and I0 in CC register). If any of these two condi-
tions is false, the interrupt is latched and thus re-
mains pending.
■ External Interrupts
External interrupts allow the processor to exit from
HALT low power mode.
External interrupt sensitivity is software selectable
through the MISCR3 register.
External interrupt triggered on edge will be latched
and the interrupt request automatically cleared
upon entering the interrupt service routine.
If several input pins of a group connected to the
same interrupt line are selected simultaneously,
these will be logically NANDed.
■ Peripheral Interrupts
Usually the peripheral interrupts cause the Device
to exit from HALT mode except those mentioned in
the “Interrupt Mapping” table.
A peripheral interrupt occurs when a specific flag
is set in the peripheral status registers and if the
corresponding enable bit is set in the peripheral
control register.
The general sequence for clearing an interrupt is
based on an access to the status register followed
by a read or write to an associated register.
Note: The clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being
serviced) will therefore be lost if the clear se-
quence is executed.
PENDING
SOFTWARE
Different
INTERRUPTS
Same
HIGHEST HARDWARE
PRIORITY SERVICED
PRIORITY
HIGHEST SOFTWARE
PRIORITY SERVICED
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