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参数资料
| 型号： | ST7FSCR1E4U1 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, QCC64 |
| 封装： | QFN-64 |
| 文件页数： | 42/101页 |
| 文件大小： | 4506K |
| 代理商： | ST7FSCR1E4U1 |
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ST7SCR1E4 ST7SCR1R4
45/101
TIMEBASE UNIT (Cont’d)
12.2.5 Low Power Modes
12.2.6 Interrupts
Note: The OVF interrupt event is connected to an
interrupt vector (see Interrupts chapter).
It generates an interrupt if the ITE bit is set in the
TBUCSR register and the I-bit in the CC register is
reset (RIM instruction).
12.2.7 Register Description
TBU COUNTER VALUE REGISTER (TBUCV)
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:0 = CV[7:0] Counter Value
This register contains the 8-bit counter value
which can be read and written anytime by soft-
ware. It is continuously incremented by hardware if
TCEN=1.
TBU CONTROL/STATUS REGISTER (TBUCSR)
Read/Write
Reset Value: 0000 0000 (00h)
Bits [7:6] = Reserved. Forced by hardware to 0.
Bit 5 = OVF Overflow Flag
This bit is set only by hardware, when the counter
value rolls over from FFh to 00h. It is cleared by
software reading the TBUCSR register. Writing to
this bit does not change the bit value.
0: No overflow
1: Counter overflow
Bit 4 = ITE Interrupt enabled.
This bit is set and cleared by software.
0: Overflow interrupt disabled
1: Overflow interrupt enabled. An interrupt request
is generated when OVF=1.
Bit 3 = TCEN TBU Enable.
This bit is set and cleared by software.
0: TBU counter is frozen and the prescaler is reset.
1: TBU counter and prescaler running.
Bits 2:0 = PR[2:0] Prescaler Selection
These bits are set and cleared by software to se-
lect the prescaling factor.
Mode
Description
WAIT
No effect on TBU
HALT
TBU halted.
Interrupt
Event
Flag
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
Counter Over-
flow Event
OVF
ITE
Yes
No
7
0
CV7
CV6
CV5
CV4
CV3
CV2
CV1
CV0
7
0
OVF
ITE
TCEN
PR2
PR1
PR0
PR2 PR1
PR0
Prescaler Division Factor
0
2
0
1
4
0
1
0
8
0
1
16
1
0
32
1
0
1
64
1
0
128
1
256
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相关代理商/技术参数 |
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