参数资料
型号: ST7FSCR1E4U1
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, QCC64
封装: QFN-64
文件页数: 32/101页
文件大小: 4506K
代理商: ST7FSCR1E4U1
ST7SCR1E4 ST7SCR1R4
36/101
I/O PORTS (Cont’d)
9.4 Register Description
DATA REGISTERS (PxDR)
Port A Data Register (PADR): 0011h
Port B Data Register (PBDR): 0015h
Port C Data Register (PCDR): 0018h
Port D Data Register (PCDR): 0019h
Read/Write
Reset Value Port A: 0000 0000 (00h)
Reset Value Port B: 0000 0000 (00h)
Reset Value Port C: 0000 0000 (00h)
Reset Value Port D: 0000 0000 (00h)
Bits 7:0 = D[7:0] Data Register 8 bits.
The DR register has a specific behaviour accord-
ing to the selected input/output configuration. Writ-
ing the DR register is always taken in account
even if the pin is configured as an input. Reading
the DR register returns either the DR register latch
content (pin configured as output) or the digital val-
ue applied to the I/O pin (pin configured as input).
DATA DIRECTION REGISTER (PADDR)
Port A Data Direction Register (PADDR): 0012h
Read/Write
Reset Value Port A: 0000 0000 (00h)
Bits 7:0 = DD7-DD0 Data Direction Register 8 bits.
The DDR register gives the input/output direction
configuration of the pins. Each bits is set and
cleared by software.
0: Input mode
1: Output mode
OPTION REGISTER (PxOR)
Port x Option Register
PxOR with x = A, B, or D
Port A Option Register (PAOR): 0013h
Port B Option Register (PBOR): 0016h
Port D Option Register (PDOR): 001Ah
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:0 = OM[7:0] Option register 8 bits.
The OR register allows to distinguish in output
mode if the push-pull or open drain configuration is
selected.
Each bit is set and cleared by software.
0: Output open drain
1: Output push-pull
PULL UP CONTROL REGISTER (PxPUCR)
Port x Pull Up Register
PxPUCR with x = A, B, or D
Port A Pull up Register (PAPUCR): 0014h
Port B Pull up Register (PBPUCR): 0017h
Port D Pull up Register (PDPUCR): 001Bh
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:0 = PU[7:0] Pull up register 8 bits.
The PU register is used to control the pull up.
Each bit is set and cleared by software.
0: Pull up inactive
1: Pull up active
7
0
D7
D6
D5
D4
D3
D2
D1
D0
7
0
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
7
0
OM7
OM6
OM5
OM4
OM3
OM2
OM1
OM0
7
0
PU7
PU6
PU5
PU4
PU3
PU2
PU1
PU0
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