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ST7SCR1E4 ST7SCR1R4
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SMARTCARD INTERFACE (Cont’d)
12.4.3.1 Power Supply Management
Smartcard Power Supply Selection
The Smartcard interface consists of a power sup-
ply output on the CRDVCC pin and a set of card in-
terface I/Os which are powered by the same rail.
The card voltage (CRDVCC) is user programma-
ble via the VCARD [1:0] bits in the CRDCR regis-
ter (refer to the Smartcard Interface section).
Four card supply voltages can be selected: 5 V,
3 V, 1.8 V or 0 V. The internal step-up converter
must be activated to supply the 5 V card voltage.
To enable the step-up converter, the user must
turn on the PLL by setting the PLL_ON bit in the
MISCR4 register. The step-up converter switching
frequency is then of 750 kHz (fOSC = 4 MHz).
Current Overload Detection and Card Removal
For each voltage, when an overload current is de-
a card is removed, the CRDVCC power supply
output is directly connected to ground.
12.4.3.2 I/O Driving Modes
Smartcard I/Os are driven in two principal modes:
– UART mode (i.e. when the UART bit of the
CRDCR register is set)
– Manual mode, driven directly by software using
the Smartcard Contact register (i.e. when the
UART bit of the CRDCR register is reset).
Card power-on activation must driven by software.
Card deactivation is handled automatically by the
Power-off functional state machine hardware.
12.4.3.3 UART Mode
Two registers are connected to the UART shift
register: CRDTXB for transmission and CRDRXB
for reception. They act as buffers to off-load the
CPU.
A parity checker and generator is coupled to the
shifter.
Character repetition and retry are supported.
The UART is in reception mode by default and
switches automatically to transmission mode
when a byte is written in the buffer.
Priority is given to transmission.
Elementary Time Unit Counter
This 11-bit counter controls the working frequency
of the UART. The operating frequency of the clock
is the same as the card clock frequency (i.e. 4
MHz).
A compensation mode can be activated via the
COMP bit of the CRDETU1 register to allow a fre-
quency granularity down to a half-etu.
Note: The decimal value is limited to a half clock
cycle. The bit duration is not fixed. It alternates be-
tween n clock cycles and n-1 clock cycles, where n
is the value to be written in the CRDETU register.
The character duration (10 bits) is also equal to
10*(n - ) clock cycles This is precise enough to
obtain the character duration specified by the
ISO7816-3 standard.
For example, if F=372 and D=32 (F being the clock
rate conversion factor and D the baud rate adjust-
ment), then etu =11.625 clock cycles.
To achieve this clock rate, compensation mode
must be activated and the etu duration must be
programmed to 12 clock cycles.
The result will be an average character duration of
11.5 clock cycles (for 10 bits).
Guardtime counter
The guardtime counter is a 9-bit counter which
manages the character frame. It controls the dura-
tion between two consecutive characters in trans-
mission.
It is incremented at the etu rate.
No guardtime is inserted for the first character
transmitted.
The guardtime between the last byte received
from the card and the next byte transmitted by the
reader must be handled by software.