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参数资料
| 型号： | ST7PL38F2MC/XXXE |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO20 |
| 封装： | 0.300 INCH, ROHS COMPLIANT, PLASTIC, SOP-20 |
| 文件页数： | 104/168页 |
| 文件大小： | 2955K |
| 代理商： | ST7PL38F2MC/XXXE |
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Obsolete
Product(s)
- Obsolete
Product(s)
ST7L34, ST7L35, ST7L38, ST7L39
40/168
POWER SAVING MODES (cont’d)
9.4 HALT MODE
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
‘HALT’ instruction when ACTIVE HALT is disabled
(see section 9.5 on page 41 for more details) and
when the AWUEN bit in the AWUCSR register is
cleared.
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see Table 6, “Interrupt
Mapping,” on page 36) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the 256
CPU cycle delay is used to stabilize the oscillator.
After the start up delay, the CPU resumes opera-
tion by servicing the interrupt or by fetching the re-
set vector which woke it up (see Figure 25).
When entering HALT mode, the I bit in the CC reg-
ister is forced to 0 to enable interrupts. Therefore,
if an interrupt is pending, the MCU wakes up im-
mediately.
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see sec-
tion 15.1 on page 154 for more details).
Figure 24. HALT Timing Overview
Figure 25. HALT Mode Flowchart
Notes:
1. WDGHALT is an option bit. See option byte section for
more details.
2. Peripheral clocked with an external clock source can
still be active.
3. Only some specific interrupts can exit the MCU from
HALT mode (such as external interrupt). Refer to Table 6,
“Interrupt Mapping,” on page 36 for more details.
4. Before servicing an interrupt, the CC register is pushed
on the stack. The I bit of the CC register is set during the
interrupt routine and cleared when the CC register is
popped.
HALT
RUN
256 or 4096 CPU
CYCLE DELAY
RESET
OR
INTERRUPT
HALT
INSTRUCTION
FETCH
VECTOR
[Active Halt disabled]
RESET
INTERRUPT 3)
Y
N
Y
CPU
OSCILLATOR
PERIPHERALS 2)
IBIT
OFF
0
OFF
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CPU
OSCILLATOR
PERIPHERALS
IBIT
ON
OFF
X 4)
ON
CPU
OSCILLATOR
PERIPHERALS
IBIT
ON
X 4)
ON
256 OR 4096 CPU CLOCK
DELAY
WATCHDOG
ENABLE
DISABLE
WDGHALT 1)
0
WATCHDOG
RESET
1
CYCLE
HALT INSTRUCTION
(Active Halt disabled)
(AWUCSR.AWUEN=0)
1
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PDF描述 |
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| ST7PL38F2UCXXXRE | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, QCC20 |
| ST7PL39F2MA/XXXE | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO20 |
| ST7L38F2UC/XXXE | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, QCC20 |
| ST7FL38F2UATRE | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, QCC20 |
| ST7PL35F2MAXXXRE | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO20 |
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