![](http://datasheet.mmic.net.cn/120000/ST7L34F2UA-XXXRE_datasheet_3577020/ST7L34F2UA-XXXRE_24.png)
Obsolete
Product(s)
- Obsolete
ST7L34, ST7L35, ST7L38, ST7L39
24/168
7 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out) and reduc-
ing the number of external components.
Main features
■ Clock Management
– 1 MHz internal RC oscillator (enabled by op-
tion byte)
– 1 to 16 MHz or 32 kHz External crystal/ceram-
ic resonator (selected by option byte)
– External Clock Input (enabled by option byte)
– PLL for multiplying the frequency by 8
■ Reset Sequence Manager (RSM)
■ System Integrity Management (SI)
– Main supply Low voltage detection (LVD) with
reset generation (enabled by option byte)
– Auxiliary Voltage detector (AVD) with interrupt
capability for monitoring the main supply (en-
abled by option byte)
7.1 INTERNAL RC OSCILLATOR ADJUSTMENT
The device contains an internal RC oscillator with
high accuracy for a given device, temperature and
voltage range (4.5V to 5.5V). It must be calibrated
to obtain the frequency required in the application.
This is done by software writing an 8-bit calibration
value in the RCCR (RC Control Register) and in
the bits [6:5] in the SICSR (SI Control/Status Reg-
ister).
Whenever the microcontroller is reset, the RCCR
returns to its default value (FFh), that is, each time
the device is reset, the calibration value must be
loaded in the RCCR. Predefined calibration values
are stored in EEPROM for 3V and 5V VDD supply
voltages at 25°C, as shown in the following table.
1. DEE0h, DEE1h, DEE2h and DEE3h addresses are lo-
cated in a reserved area but are special bytes containing
also the RC calibration values which are read-accessible
only in user mode. If all the EEPROM data or Flash space
(including the RC calibration values locations) has been
erased (after the readout protection removal), then the RC
calibration values can still be obtained through these four
addresses.
For compatibility reasons with the SICSR register, CR[1:0]
bits are stored in the fifth and sixth positions of DEE1 and
DEE3 addresses.
Notes:
– In ICC mode, the internal RC oscillator is forced
as a clock source, regardless of the selection in
the option byte.
page 127 for more information on the frequency
and accuracy of the RC oscillator.
– To improve clock stability and frequency accura-
cy, it is recommended to place a decoupling ca-
pacitor, typically 100nF, between the VDD and
VSS pins as close as possible to the ST7 device.
– These bytes are systematically programmed by
ST, including on FASTROM devices. Conse-
quently, customers intending to use FASTROM
service must not use these bytes.
– RCCR0 and RCCR1 calibration values will not
be erased if the readout protection bit is reset af-
Caution: If the voltage or temperature conditions
change in the application, the frequency might
need recalibration.
Refer to application note AN1324 for information
on how to calibrate the RC frequency using an ex-
ternal reference signal.
7.2 PHASE LOCKED LOOP
The PLL can be used to multiply a 1 MHz frequen-
cy from the RC oscillator or the external clock by 8
to obtain fOSC of 8 MHz. The PLL is enabled (by 1
option bit) and the multiplication factor is 8.
The x8 PLL is intended for operation with VDD in
the option byte description).
If the PLL is disabled and the RC oscillator is ena-
bled, then fOSC = 1 MHz.
If both the RC oscillator and the PLL are disabled,
fOSC is driven by the external clock.
RCCR
Conditions
ST7L3
Addresses
RCCRH0
VDD = 5V
TA = 25°C
fRC = 1 MHz
DEE0h1) (CR[9:2] bits)
RCCRL0
DEE1h1) (CR[1:0] bits)
RCCRH1
VDD = 3.3V
TA = 25°C
fRC = 1 MHz
DEE2h1) (CR[9:2] bits)
RCCRL1
DEE3h1) (CR[1:0] bits)
1