参数资料
型号: ST7PL38F2MC/XXXE
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO20
封装: 0.300 INCH, ROHS COMPLIANT, PLASTIC, SOP-20
文件页数: 7/168页
文件大小: 2955K
代理商: ST7PL38F2MC/XXXE
Obsolete
Product(s)
- Obsolete
Product(s)
ST7L34, ST7L35, ST7L38, ST7L39
104/168
LINSCI
SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
11.5.9.3 LIN Reception
In LIN mode the reception of a byte is the same as
in SCI mode but the LINSCI has features for han-
dling the LIN Header automatically (identifier de-
tection) or semiautomatically (Synch Break detec-
tion) depending on the LIN Header detection
mode. The detection mode is selected by the
LHDM bit in the SCICR3.
Additionally, an automatic resynchronization fea-
ture can be activated to compensate for any clock
deviation, for more details please refer to Section
LIN Header Handling by a Slave
Depending on the LIN Header detection method
the LINSCI will signal the detection of a LIN Head-
er after the LIN Synch Break or after the Identifier
has been successfully received.
Note:
It is recommended to combine the Header detec-
tion function with Mute mode. Putting the LINSCI
in Mute mode allows the detection of Headers only
and prevents the reception of any other charac-
ters.
This mode can be used to wait for the next Header
without being interrupted by the data bytes of the
current message in case this message is not rele-
vant for the application.
Synch Break Detection (LHDM = 0):
When a LIN Synch Break is received:
– The RDRF bit in the SCISR register is set. It in-
dicates that the content of the shift register is
transferred to the SCIDR register, a value of
0x00 is expected for a Break.
– The LHDF flag in the SCICR3 register indicates
that a LIN Synch Break Field has been detected.
– An interrupt is generated if the LHIE bit in the
SCICR3 register is set and the I[1:0] bits are
cleared in the CCR register.
– Then the LIN Synch Field is received and meas-
ured.
– If automatic resynchronization is enabled (LA-
SE bit = 1), the LIN Synch Field is not trans-
ferred to the shift register: There is no need to
clear the RDRF bit.
– If automatic resynchronization is disabled (LA-
SE bit = 0), the LIN Synch Field is received as
a normal character and transferred to the
SCIDR register and RDRF is set.
Note:
In LIN slave mode, the FE bit detects all frame er-
ror which does not correspond to a break.
Identifier Detection (LHDM = 1):
This case is the same as the previous one except
that the LHDF and the RDRF flags are set only af-
ter the entire header has been received (this is
true whether automatic resynchronization is ena-
bled or not). This indicates that the LIN Identifier is
available in the SCIDR register.
Notes:
During LIN Synch Field measurement, the SCI
state machine is switched off: No characters are
transferred to the data register.
LIN Slave parity
In LIN Slave mode (LINE and LSLV bits are set)
LIN parity checking can be enabled by setting the
PCE bit.
In this case, the parity bits of the LIN Identifier
Field are checked. The identifier character is rec-
ognized as the third received character after a
break character (included):
The bits involved are the two MSB positions (7th
and 8th bits if M = 0; 8th and 9th bits if M = 0) of
the identifier character. The check is performed as
specified by the LIN specification:
LIN Synch
Identifier
parity bits
Field
Break
Identifier Field
parity bits
ID0
start bit
stop bit
ID1 ID2 ID3 ID4 ID5 P0 P1
identifier bits
P1
ID1
ID3
ID4
ID5
⊕⊕
=
P0
ID0
=
ID1
ID2
ID4
⊕⊕
M= 0
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