参数资料
型号: ST7PL38F2MC/XXXE
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO20
封装: 0.300 INCH, ROHS COMPLIANT, PLASTIC, SOP-20
文件页数: 117/168页
文件大小: 2955K
代理商: ST7PL38F2MC/XXXE
Obsolete
Product(s)
- Obsolete
Product(s)
ST7L34, ST7L35, ST7L38, ST7L39
52/168
WATCHDOG TIMER (cont’d)
The application program must write in the CR reg-
ister at regular intervals during normal operation to
prevent an MCU reset. This downcounter is free-
running: It counts down even if the watchdog is
disabled. The value to be stored in the CR register
must be between FFh and C0h (see Table 14
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an imme-
diate reset
– The T[5:0] bits contain the number of increments
which represents the time delay before the
watchdog produces a reset.
Following a reset, the watchdog is disabled. Once
activated it cannot be disabled, except by a reset.
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
If the watchdog is activated, the HALT instruction
will generate a Reset.
Table 14.Watchdog Timing
Note: The timing variation shown in Table 14 is
due to the unknown status of the prescaler when
writing to the CR register.
11.1.4 Hardware Watchdog Option
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the CR is not used.
Refer to the Option Byte description in section
11.1.4.1 Using Halt Mode with the WDG
(WDGHALT option)
If Halt mode with Watchdog is enabled by option
byte (No watchdog reset on HALT instruction), it is
recommended before executing the HALT instruc-
tion to refresh the WDG counter, to avoid an unex-
pected WDG reset immediately after waking up
the microcontroller.
11.1.5 Interrupts
None.
11.1.6 Register Description
WATCHDOG CONTROL REGISTER (WDGCR)
Read/Write
Reset Value: 0111 1111 (7Fh)
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note: This bit is not used if the hardware watch-
dog option is enabled by option byte.
Bits 6:0 = T[6:0] 7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
Table 15. Watchdog Timer Register Map and Reset Values
fCPU = 8 MHz
WDG
Counter
Code
min
(ms)
max
(ms)
C0h
1
2
FFh
127
128
70
WDGA
T6
T5
T4
T3
T2
T1
T0
Address
(Hex.)
Register
Label
765
4321
0
002Eh
WDGCR
Reset Value
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
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