参数资料
型号: ST7PL38F2MC/XXXE
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO20
封装: 0.300 INCH, ROHS COMPLIANT, PLASTIC, SOP-20
文件页数: 129/168页
文件大小: 2955K
代理商: ST7PL38F2MC/XXXE
Obsolete
Product(s)
- Obsolete
Product(s)
ST7L34, ST7L35, ST7L38, ST7L39
63/168
DUAL 12-BIT AUTORELOAD TIMER 3 (cont’d)
11.2.6 Register Description
TIMER CONTROL/STATUS REGISTER
(ATCSR)
Read / Write
Reset Value: 0x00 0000 (x0h)
Bit 7 = Reserved
Bit 6 = ICF Input Capture Flag
This bit is set by hardware and cleared by software
by reading the ATICR register (a read access to
ATICRH or ATICRL will clear this flag). Writing to
this bit does not change the bit value.
0: No input capture
1: An input capture has occurred
Bit 5 = ICIE IC Interrupt Enable
This bit is set and cleared by software.
0: Input capture interrupt disabled
1: Input capture interrupt enabled
Bits 4:3 = CK[1:0] Counter Clock Selection
These bits are set and cleared by software and
cleared by hardware after a reset. They select the
clock frequency of the counter.
Bit 2 = OVF1 Overflow Flag
This bit is set by hardware and cleared by software
by reading the TCSR register. It indicates the tran-
sition of the counter1 CNTR1 from FFh to ATR1
value.
0: No counter overflow occurred
1: Counter overflow occurred
Bit 1 = OVFIE1 Overflow Interrupt Enable
This bit is read/write by software and cleared by
hardware after a reset.
0: Overflow interrupt disabled
1: Overflow interrupt enabled
Bit 0 = CMPIE Compare Interrupt Enable
This bit is read/write by software and cleared by
hardware after a reset. It can be used to mask the
interrupt generated when any of the CMPFx bit is
set.
0: Output compare interrupt disabled
1: Output compare interrupt enabled
COUNTER REGISTER 1 HIGH (CNTR1H)
Read only
Reset Value: 0000 0000 (000h)
COUNTER REGISTER 1 LOW (CNTR1L)
Read only
Reset Value: 0000 0000 (000h)
Bits 15:12 = Reserved
Bits 11:0 = CNTR1[11:0] Counter Value
This 12-bit register is read by software and cleared
by hardware after a reset. The counter is incre-
mented continuously as soon as a counter clock is
selected. To obtain the 12-bit value, software
should read the counter value in two consecutive
read operations. The CNTR1H register can be in-
cremented between the two reads, and in order to
be accurate when fTIMER =fCPU, the software
should take this into account when CNTR1L and
CNTR1H are read. If CNTR1L is close to its high-
est value, CNTR1H could be incremented before it
is read.
When a counter overflow occurs, the counter re-
starts from the value specified in the ATR1 regis-
ter.
76
0
ICF
ICIE
CK1
CK0
OVF1 OVFIE1 CMPIE
Counter Clock Selection
CK1
CK0
OFF
0
OFF
1
fLTIMER (1ms timebase @ 8 MHz)
0
1
fCPU
10
15
8
00
CNTR1_
11
CNTR1_
10
CNTR1_
9
CNTR1_
8
70
CNTR1_
7
CNTR1_
6
CNTR1_
5
CNTR1_
4
CNTR1_
3
CNTR1_
2
CNTR1_
1
CNTR1_
0
1
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