参数资料
型号: TMS320C2812ZHHS
厂商: TEXAS INSTRUMENTS INC
元件分类: 数字信号处理
英文描述: 16-BIT, 150 MHz, OTHER DSP, PBGA179
封装: LEAD FREE, BGA-179
文件页数: 14/156页
文件大小: 1826K
代理商: TMS320C2812ZHHS
Electrical Specifications
110
April 2001 Revised October 2005
SPRS174M
Table 614. HALT Mode Timing Requirements
MIN
NOM
MAX
UNIT
tw(WAKE-XNMI)
Pulse duration, XNMI wakeup signal
2tc(CI)
Cycles
tw(WAKE-XRS)
Pulse duration, XRS wakeup signal
8tc(CI)
Cycles
Table 615. HALT Mode Switching Characteristics
PARAMETER
MIN
TYP
MAX
UNIT
td(IDLE-XCOH)
Delay time, IDLE instruction executed to XCLKOUT high
32tc(SCO)
45tc(SCO)
Cycles
tp
PLL lock-up time
131 072tc(CI) Cycles
Delay time, PLL lock to program execution resume
td(wake)
Wake-up from flash
Flash module in sleep state
1125tc(SCO) Cycles
Wake-up from SARAM
35tc(SCO) Cycles
XCLKOUT = SYSCLKOUT
NOTES: A. IDLE instruction is executed to put the device into HALT mode.
B. The PLL block responds to the HALT signal. SYSCLKOUT is held for another 32 cycles before the oscillator is turned off and the
CLKIN to the core is stopped. This 32-cycle delay enables the CPU pipe and any other pending operations to flush properly.
C. Clocks to the peripherals are turned off and the internal oscillator and PLL are shut down. The device is now in HALT mode and
consumes absolute minimum power.
D. When XNMI is driven active (negative edge triggered shown , as an example), the oscillator is turned on; but the PLL is not
activated.
E. When XNMI is deactivated, it initiates the PLL lock sequence, which takes 131,072 X1/XCLKIN cycles.
F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT mode is now
exited.
G. Normal operation resumes.
td(IDLEXCOH)
32 SYSCLKOUT Cycles
X1/XCLKIN
XCLKOUT
HALT
Wake-up Latency
Flushing Pipeline
td(wake)
A
B
C
D
Device
Status
E
G
F
PLL Lock-up Time
XNMI
Normal
Execution
tw(WAKE-XNMI)
tp
Oscillator Start-up Time
Figure 616. HALT Wakeup Using XNMI
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