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参数资料
型号： TMS320C2812ZHHS
厂商： TEXAS INSTRUMENTS INC
元件分类： 数字信号处理
英文描述： 16-BIT, 150 MHz, OTHER DSP, PBGA179
封装： LEAD FREE, BGA-179
文件页数： 28/156页
文件大小： 1826K
代理商： TMS320C2812ZHHS
Electrical Specifications
123
April 2001 Revised October 2005
SPRS174M
6.22
External Interface (XINTF) Timing
Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures the Lead/Active/Trail
wait states in the XTIMING registers. There is one XTIMING register for each XINTF zone. Table 628 shows
the relationship between the parameters configured in the XTIMING register and the duration of the pulse in
terms of XTIMCLK cycles.
Table 628. Relationship Between Parameters Configured in XTIMING and Duration of Pulse
DESCRIPTION
DURATION (ns)
DESCRIPTION
X2TIMING = 0
X2TIMING = 1
LR
Lead period, read access
XRDLEAD
× tc(XTIM)
(XRDLEAD
× 2) × tc(XTIM)
AR
Active period, read access
(XRDACTIVE + WS + 1)
× tc(XTIM)
(XRDACTIVE
× 2 + WS + 1) × tc(XTIM)
TR
Trail period, read access
XRDTRAIL
× tc(XTIM)
(XRDTRAIL
× 2) × tc(XTIM)
LW
Lead period, write access
XWRLEAD
× tc(XTIM)
(XWRLEAD
× 2) × tc(XTIM)
AW
Active period, write access
(XWRACTIVE + WS + 1)
× tc(XTIM)
(XWRACTIVE
× 2 + WS + 1) × tc(XTIM)
TW
Trail period, write access
XWRTRAIL
× tc(XTIM)
(XWRTRAIL
× 2) × tc(XTIM)
tc(XTIM) Cycle time, XTIMCLK
WS refers to the number of wait states inserted by hardware when using XREADY. If the zone is configured to ignore XREADY (USEREADY = 0),
then WS = 0.
Minimum wait state requirements must be met when configuring each zone’s XTIMING register. These
requirements are in addition to any timing requirements as specified by that device’s data sheet. No internal
device hardware is included to detect illegal settings.
If the XREADY signal is ignored (USEREADY = 0), then:
1.
Lead:
LR
≥ tc(XTIM)
LW
≥ tc(XTIM)
These requirements result in the following XTIMING register configuration restrictions§:
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥ 1
≥ 0
≥ 1
≥ 0
0, 1
§ No hardware to detect illegal XTIMING configurations
Examples of valid and invalid timing when not sampling XREADY§:
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
Invalid
0
0, 1
Valid
1
0
1
0
0, 1
§ No hardware to detect illegal XTIMING configurations
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