参数资料
型号: TMS320C2812ZHHS
厂商: TEXAS INSTRUMENTS INC
元件分类: 数字信号处理
英文描述: 16-BIT, 150 MHz, OTHER DSP, PBGA179
封装: LEAD FREE, BGA-179
文件页数: 36/156页
文件大小: 1826K
代理商: TMS320C2812ZHHS
Electrical Specifications
130
April 2001 Revised October 2005
SPRS174M
Lead
Active
Trail
DIN
td(XCOH-XZCSL)
td(XCOH-XA)
td(XCOHL-XRDL)
td(XCOHL-XZCSH)
td(XCOHL-XRDH)
WS (Synch)
XCLKOUT=XTIMCLK
XCLKOUT=1/2 XTIMCLK
XZCS0AND1, XZCS2,
XZCS6AND7
XA[0:18]
XRD
XWE
XR/W
XD[0:15]
XREADY(Synch)
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes
alignment cycles.
D. For each sample, setup time from the beginning of the access (D) can be calculated as:
D = (XRDLEAD + XRDACTIVE +n 1) tc(XTIM) tsu(XRDYsynchL)XCOHL
E. Reference for the first sample is with respect to this point
E = (XRDLEAD + XRDACTIVE) tc(XTIM)
where n is the sample number: n = 1, 2, 3, and so forth.
th(XRDYsynchL)
tsu(XRDYsynchL)XCOHL
tsu(XD)XRD
ta(XRD)
ta(A)
th(XD)XRD
th(XRDYsynchH)XZCSH
= Don’t care. Signal can be high or low during this time.
Legend:
tsu(XRDHsynchH)XCOHL
See Note D
See Note E
te(XRDYsynchH)
See Note D
See Notes A and B
See Note C
Figure 632. Example Read With Synchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
≥1
3
≥1
1
0
N/A
0 = XREADY
(Synch)
N/A = “Don’t care” for this example
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