参数资料
型号: TMS320C2812ZHHS
厂商: TEXAS INSTRUMENTS INC
元件分类: 数字信号处理
英文描述: 16-BIT, 150 MHz, OTHER DSP, PBGA179
封装: LEAD FREE, BGA-179
文件页数: 56/156页
文件大小: 1826K
代理商: TMS320C2812ZHHS
Electrical Specifications
149
April 2001 Revised October 2005
SPRS174M
6.31.2
McBSP as SPI Master or Slave Timing
Table 649. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
NO.
MASTER
SLAVE
UNIT
NO.
MIN
MAX
MIN
MAX
UNIT
M30
tsu(DRV-CKXL)
Setup time, DR valid before CLKX low
30
8P10
ns
M31
th(CKXL-DRV)
Hold time, DR valid after CLKX low
1
8P10
ns
M32
tsu(BFXL-CKXH)
Setup time, FSX low before CLKX high
8P+10
ns
M33
tc(CKX)
Cycle time, CLKX
2P
16P
ns
Table 650. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
NO.
PARAMETER
MASTER
SLAVE
UNIT
NO.
PARAMETER
MIN
MAX
MIN
MAX
UNIT
M24
th(CKXL-FXL)
Hold time, FSX low after CLKX low
2P
ns
M25
td(FXL-CKXH)
Delay time, FSX low to CLKX high
P
ns
M28
tdis(FXH-DXHZ)
Disable time, DX high impedance following
last data bit from FSX high
6
6P + 6
ns
M29
td(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With
maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.6875 MHz and P =13.3 ns.
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
CLKX
FSX
DX
M30
M31
DR
M28
M24
M29
M25
LSB
MSB
M32
M33
Figure 644. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
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