TMS320LF2407A,TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145K JULY 2000 REVISED AUGUST 2005
108
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
10-bit analog-to-digital converter (ADC) (continued)
operating characteristics over recommended operating condition ranges
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
VCCA = 3.3 V
10
15
mA
ICCA
Analog supply current
VCCA = VREFHI = 3.3 V
PLL or OSC power
down
1
A
IADREFHI
VREFHI input current
0.75
1.5
mA
IADCIN
Analog input leakage
1
A
C
Analog input capacitance
Typical capacitive load on
Non-sampling
10
pF
Cai
Analog input capacitance
Typical capacitive load on
analog input pin
Sampling
30
pF
td(PU)
Delay time, power-up to ADC valid
Time to stabilize analog stage after power-up
10
s
ZAI
Analog input source impedance
Analog input source impedance needed for
conversions to remain within specifications at min
tw(SH)
53
10
Zero-offset error
"2
LSB
Absolute resolution = 3.22 mV. At VREFHI = 3.3 V and VREFLO = 0 V, this is one LSB. As VREFHI decreases, VREFLO increases, or both, the LSB
size decreases. Therefore, the absolute accuracy and differential/integral linearity errors in terms of LSBs increase.
EDNL and EINL
PARAMETER
DESCRIPTION
CLKOUT
MIN
MAX
UNIT
EDNL
Differential nonlinearity error
Difference between the actual step width
and the ideal value
30 MHz
"2
LSB
EINL
Integral nonlinearity error
Maximum deviation from the best straight
line through the ADC transfer
characteristics, excluding the quantization
error
30 MHz
"2
LSB
Test conditions: VREFHI = VCCA , VREFLO = VSSA