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参数资料
| 型号： | TMX320LF2403AVFS |
| 厂商： | Texas Instruments, Inc. |
| 元件分类： | 数字信号处理 |
| 英文描述： | DSP CONTROLLERS |
| 中文描述： | DSP控制器 |
| 文件页数： | 84/134页 |
| 文件大小： | 1759K |
| 代理商： | TMX320LF2403AVFS |
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TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145K JULY 2000 REVISED AUGUST 2005
53
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
serial communications interface (SCI) module
The 240xA devices include a serial communications interface (SCI) module. The SCI module supports digital
communications between the CPU and other asynchronous peripherals that use the standard
non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own
separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex
mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing
errors. The bit rate is programmable to over 65000 different speeds through a 16-bit baud-select register.
Features of the SCI module include:
D Two external pins:
SCITXD: SCI transmit-output pin
SCIRXD: SCI receive-input pin
NOTE: Both pins can be used as GPIO if not used for SCI.
D Baud rate programmable to 64K different rates
Up to 2500 Kbps at 40-MHz CPUCLK
D Data-word format
One start bit
Data-word length programmable from one to eight bits
Optional even/odd/no parity bit
One or two stop bits
D Four error-detection flags: parity, overrun, framing, and break detection
D Two wake-up multiprocessor modes: idle-line and address bit
D Half- or full-duplex operation
D Double-buffered receive and transmit functions
D Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and
TX EMPTY flag (transmitter-shift register is empty)
Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag
(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
D Separate enable bits for transmitter and receiver interrupts (except BRKDT)
D NRZ (non-return-to-zero) format
D Ten SCI module control registers located in the control register frame beginning at address 7050h
NOTE: All registers in this module are 8-bit registers that are connected to the 16-bit peripheral bus. When a register is accessed, the
register data is in the lower byte (7 0), and the upper byte (15 8) is read as zeros. Writing to the upper byte has no effect.
Figure 14 shows the SCI module block diagram.
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| TMX320LF2404APAGA | DSP CONTROLLERS |
| TMX320LF2404APAGS | DSP CONTROLLERS |
| TMX320LF2404APGA | DSP CONTROLLERS |
| TMX320LF2404APGEA | DSP CONTROLLERS |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TMX320LF2404APAGA | 制造商:TI 制造商全称:Texas Instruments 功能描述:DSP CONTROLLERS |
| TMX320LF2404APAGS | 制造商:TI 制造商全称:Texas Instruments 功能描述:DSP CONTROLLERS |
| TMX320LF2404APGA | 制造商:TI 制造商全称:Texas Instruments 功能描述:DSP CONTROLLERS |
| TMX320LF2404APGEA | 制造商:TI 制造商全称:Texas Instruments 功能描述:DSP CONTROLLERS |
| TMX320LF2404APGES | 制造商:TI 制造商全称:Texas Instruments 功能描述:DSP CONTROLLERS |
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