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参数资料
型号： TMX320LF2403AVFS
厂商： Texas Instruments, Inc.
元件分类： 数字信号处理
英文描述： DSP CONTROLLERS
中文描述： DSP控制器
文件页数： 94/134页
文件大小： 1759K
代理商： TMX320LF2403AVFS
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145K JULY 2000 REVISED AUGUST 2005
62
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
description of shared I/O pins (continued)
Table 12. Shared Pin Configurations
PIN FUNCTION SELECTED
MUX
CONTROL
MUX CONTROL
I/O PORT DATA AND DIRECTION
(MCRx.n = 1)
Primary Function
(MCRX.N = 0)
I/O
CONTROL
REGISTER
(name.bit #)
MUX CONTROL
VALUE AT RESET
(MCRx.n)
REGISTER
DATA BIT NO.§
DIR BIT NO.
PORT A
SCITXD
IOPA0
MCRA.0
0
PADATDIR
0
8
SCIRXD
IOPA1
MCRA.1
0
PADATDIR
1
9
XINT1
IOPA2
MCRA.2
0
PADATDIR
2
10
CAP1/QEP1
IOPA3
MCRA.3
0
PADATDIR
3
11
CAP2/QEP2
IOPA4
MCRA.4
0
PADATDIR
4
12
CAP3
IOPA5
MCRA.5
0
PADATDIR
5
13
PWM1
IOPA6
MCRA.6
0
PADATDIR
6
14
PWM2
IOPA7
MCRA.7
0
PADATDIR
7
15
PORT B
PWM3
IOPB0
MCRA.8
0
PBDATDIR
0
8
PWM4
IOPB1
MCRA.9
0
PBDATDIR
1
9
PWM5
IOPB2
MCRA.10
0
PBDATDIR
2
10
PWM6
IOPB3
MCRA.11
0
PBDATDIR
3
11
T1PWM/T1CMP
IOPB4
MCRA.12
0
PBDATDIR
4
12
T2PWM/T2CMP
IOPB5
MCRA.13
0
PBDATDIR
5
13
TDIRA
IOPB6
MCRA.14
0
PBDATDIR
6
14
TCLKINA
IOPB7
MCRA.15
0
PBDATDIR
7
15
PORT C
W/R #
IOPC0
MCRB.0
1
PCDATDIR
0
8
BIO
IOPC1
MCRB.1
1
PCDATDIR
1
9
SPISIMO
IOPC2
MCRB.2
0
PCDATDIR
2
10
SPISOMI
IOPC3
MCRB.3
0
PCDATDIR
3
11
SPICLK
IOPC4
MCRB.4
0
PCDATDIR
4
12
SPISTE
IOPC5
MCRB.5
0
PCDATDIR
5
13
CANTX
IOPC6
MCRB.6
0
PCDATDIR
6
14
CANRX
IOPC7
MCRB.7
0
PCDATDIR
7
15
PORT D
XINT2/ADCSOC
IOPD0
MCRB.8
0
PDDATDIR
0
8
EMU0
Reserved
MCRB.9||
1
PDDATDIR
1
9
EMU1
Reserved
MCRB.10||
1
PDDATDIR
2
10
TCK
Reserved
MCRB.11||
1
PDDATDIR
3
11
TDI
Reserved
MCRB.12||
1
PDDATDIR
4
12
TDO
Reserved
MCRB.13||
1
PDDATDIR
5
13
TMS
Reserved
MCRB.14||
1
PDDATDIR
6
14
TMS2
Reserved
MCRB.15||
1
PDDATDIR
7
15
Bold, italicized pin names indicate pin functions at reset.
Valid only if the I/O function is selected on the pin
§ If the GPIO pin is configured as an output, these bits can be written to. If the pin is configured as an input, these bits are read from.
If the DIR bit is 0, the GPIO pin functions as an input. For a value of 1, the pin is configured as an output.
# At reset, all LF240xA devices come up with the W/R/IOPC0 pin in W/R mode. On devices that lack an external memory interface (e.g., LF2406A),
W/R mode is not functional and MCRB.0 must be set to a 0 if the IOPC0 pin is to be used. The XMIF Hi-Z control bit (bit 4 of the SCSR2 register)
is reserved in these devices and must be written with a zero.
|| Bits 15 through 9 of the MCRB register must be written as 1 only. Writing a 0 to any of these bits will cause unpredictable operation of the device.
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