TMS320LF2407A,TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145K JULY 2000 REVISED AUGUST 2005
95
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
SPI slave mode timing parameters
Slave mode timing information is listed in the following tables.
SPI slave mode external timing parameters (clock phase = 0) (see Figure 43)
NO.
MIN
MAX
UNIT
12
tc(SPC)S
Cycle time, SPICLK
4tc(CO)
ns
13§
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)S10
0.5tc(SPC)S
13§
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 1)
0.5tc(SPC)S10
0.5tc(SPC)S
ns
14§
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 0)
0.5tc(SPC)S10
0.5tc(SPC)S
14§
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 1)
0.5tc(SPC)S10
0.5tc(SPC)S
ns
15§
td(SPCH-SOMI)S
Delay time, SPICLK high to SPISOMI valid
(clock polarity = 0)
0.375tc(SPC)S10
ns
15§
td(SPCL-SOMI)S
Delay time, SPICLK low to SPISOMI valid (clock polarity = 1)
0.375tc(SPC)S10
ns
16§
tv(SPCL-SOMI)S
Valid time, SPISOMI data valid after SPICLK low
(clock polarity =0)
0.75tc(SPC)S
16§
tv(SPCH-SOMI)S
Valid time, SPISOMI data valid after SPICLK high
(clock polarity =1)
0.75tc(SPC)S
ns
19§
tsu(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK low (clock polarity = 0)
0
19§
tsu(SIMO-SPCH)S
Setup time, SPISIMO before SPICLK high (clock polarity = 1)
0
ns
20§
tv(SPCL-SIMO)S
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 0)
0.5tc(SPC)S
ns
20§
tv(SPCH-SIMO)S
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 1)
0.5tc(SPC)S
ns
The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc = system clock cycle time = 1/CLKOUT = tc(CO)
§ The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).