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参数资料
| 型号： | TSB43AA82GGW |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PBGA176 |
| 封装： | PLASTIC, BGA-176 |
| 文件页数： | 113/146页 |
| 文件大小： | 770K |
| 代理商： | TSB43AA82GGW |
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43
4.2.3
Exception to the Rule
By intentionally controlling tLabel, the response of a request packet from the ATF can be received by the DRF. This
method can be used when the size of a response packet is larger than the size of the ARF. As shown below, a request
packet with tlabel 01_xxxx is transmitted from the ATF but received by the DRF.
PACKET INPUT THROUGH 70h to 78h
FIFOs
tLabel
tCode
Transmit FIFO
Receive FIFO
01_xxxx
Request packet
ATF
DRF
NOTE: Combinations other than that specified are not recommended.
4.3
Asynchronous Transmit FIFO (ATF)
Asynchronous transmit refers to the use of the ATF interface. It is configurable in register 2Ch (ATF satus register).
To transmit packets, the 1394 asynchronous headers and the data are loaded into the ATF interface by the host. The
host accesses the ATF FIFO through registers 70h78h with the appropriate tLabel and tCode described in
Section 4.2. The asynchronous header must fit the form described in Section 4.3.1.
4.3.1
Generic Quadlet and Block Transmit
The quadlet-transmit format is shown in Figure 41. The first quadlet contains packet control information. The second
and third quadlets contain the 64-bit, quadlet-aligned address. The fourth quadlet is data used only for write requests
and read responses. For read requests and write responses, the quadlet data field is omitted.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved
spd
tLabel
rt
tCode
prior
destination ID
destination_offset_high
destination_offset_low
quadlet data
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Figure 41. Generic Transmit Format of Packet With Quadlet Data
The block-transmit format is shown in Figure 42 and a description of each field is shown in Table 41. The first
quadlet contains packet-control information. The second quadlet contains the bus and node number of the destination
node, and the last 16 bits of the second quadlet and all of the third quadlet contain the 48-bit quadlet-aligned
destination offset address. The first 16 bits of the fourth quadlet contains the size of the data in the packet. The
remaining 16 bits of the fourth quadlet represent the extended_tCode field (see Table 6-10 of the IEEE 1394-1995
standard for more information on extended tCodes). The block data, if any, follows the extended_tCode.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved
spd
tLabel
rt
tCode
prior
destination ID
destination_offset_high
destination_offset_low
data_length
extended_tCode
block data
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Figure 42. Generic Transmit Format of Packet With Block Data
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TSB43AA82GHH | 制造商:Texas Instruments 功能描述: |
| TSB43AA82I | 制造商:TI 制造商全称:Texas Instruments 功能描述:1394 INTEGRATED PHY AND LINK LAYER CONTROLLER |
| TSB43AA82IGGW | 功能描述:1394 接口集成电路 2Port Hi Perf Integ Phy&Link Layer Chip RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB43AA82PGE | 功能描述:1394 接口集成电路 2Port Hi Perf Integ Phy&Link Layer Chip RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB43AA82PGEG4 | 功能描述:1394 接口集成电路 2Port Hi Per Int Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
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