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参数资料
型号： TSB43AA82GGW
厂商： TEXAS INSTRUMENTS INC
元件分类： 微控制器/微处理器
英文描述： 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PBGA176
封装： PLASTIC, BGA-176
文件页数： 75/146页
文件大小： 770K
代理商： TSB43AA82GGW
38
3.4.3
Control Register at 08h
This register defaults to 4400 CA00h and is unaffected by a bus reset.
BITS
ACRONYM
DIR
DESCRIPTION
0
IDVal
R/O
ID valid. The IDVal bit is set to 1 when the information of the bus reset register at 24h is valid. This bit
defaults to 0 and is automatically set by the hardware on a bus reset.
1
RxSId
R/W
Receive self-identification (self-ID) packets. When set to 1, the self-ID packets generated by the PHY
during bus initialization are received and written to DRF or LOG as individual packets. Otherwise the
self-ID packets are not received. This bit defaults to 1 and is unaffected by a bus reset.
2
RSIsel
R/W
Received self-ID packet location selection. If RxSId is set to 1, the received self-ID packets are verified and
written to the DRF when RSIsel is set to 1 and are verified and written to the LOG when RSIsel is set to 0.
3
Reserved
N/A
Reserved
4
Bsy0
R/W
Busy control. When this bit is set to 1, the ack_busy_X is sent to all incoming packets. When Bsy0 is set to
0, ack_busy_X is sent according to the normal busy/retry protocol.
5
TrEn
R/W
Transactions enable. When TrEn is set to 1, the transmitter and receiver are enabled to transmit and
receive packets. When TrEn is set to 0, the link core is not awake, the TSB43AA82 cannot send ack or
receive self-ID packets, and the transmitter and receiver are disabled. This bit defaults to 1 and is
unaffected by a bus reset.
6
Reserved
N/A
Reserved
7
ACArbOn
R/W
Accelerated arbitration on. When ACArbOn is set to 1, accelerated arbitration is enabled.
89
Reserved
N/A
Reserved
10
RstTr
S/C
Reset transaction. When RstTr is set to 1, the entire transaction in the ATF, the ARF, the CTQ, the CRF, the
MTQ, and the MRF resets synchronously. This does not affect the DTF and the DRF.
1113
Reserved
N/A
Reserved
14
ErrResp
R/W
Error packet response. When ErrResp is set to 1, packets with errors are returned an ack_pending in the
response packet. When ErrResp is set to 0, packets with errors are returned an ack error code in the
response packet.
15
StErpkt
R/W
Store error packets. When StErpkt is set to1, packets with any errors are stored.
16
SplTrEn
R/W
Split transaction enable. When SplTrEn is set to 1, split transactions are enabled. The ATF timer attempts a
split transaction for the received ack_pending and cannot transmit any packets until the response packet
is received or a split-time out occurs. When SplTrEn is set to 0, split transactions are disabled. This bit
defaults to 1 and is unaffected by a bus reset.
17
RetryEn
R/W
Automatic retry enable. When set to 1, the ATF retries automatically when ack_busy_X, ack_busy_A or
ack_busy_B is received. This bit defaults to 1 and is unaffected by a bus reset.
18
Ackpnd
R/W
Ack pending enable. When Ackpnd is set to 1, the receiver sends ack_pending instead of ack_complete to
the write request packets. When Ackpnd is set to 0, the receiver sends ack_complete to the write request
packets.
19
MAAckConf
R/W
Management ack_Conflict_Error enable. When MAAckConf is set to 1, ack_conflict_error is sent instead
of ack_busy when MagtBsy at 44h bit 1 is set to 1. When MAAckConf is set to 0, ack_busy is sent. This bit
is the same as MAAckConf at 18h bit 14.
20
CyMas
R/W
Cycle master. When CyMas is set to 1 and this chip is the root PHY, the cycle master function is enabled.
When CyMas is set to 0, the cyclemaster function is disabled. This bit defaults to 1 and is unaffected by a
bus reset.
21
Reserved
N/A
Reserved
22
CyTmrEn
R/W
Cycle-timer enable. When CyTmrEn is set to 1, the cycle_offset field increments. This bit defaults to 1 and
is unaffected by a bus reset.
23
DMclr
S/C
DMA block clear. When DMClr is set to 1, all the states in the DMA block are reset synchronously. Clear the
DMA, DTF, and DRF prior to clearing the DMA.
24
RxUnexp
R/W
Received unexpected response packets. When set to 1, unexpected response packets are received and
written to the ARF or the DRF. When set to 0, unexpected response packets are not received.
25
RUEsel
R/W
Receive unexpected response packets select. Select either the ARF or DRF to place the unexpected
response packets. When RxUnexp is set to 1 and RUEsel is set to 1, the unexpected response packets,
such as a write request packet to a read-only register or a read request to a write-only register, are written
to the DRF.
When RxUnexp is set to 1 and RUEsel is set to 0, the unexpected response packets are written to ARF.
When RxUnexp is set to 0, RUEsel is invalid.
2631
Prio_Budget
R/W
Priority budget counter. Prio_Budget value loaded to the priority budget counter.
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TSB43AA82PGEG4 功能描述:1394 接口集成电路 2Port Hi Per Int Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray
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