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参数资料
| 型号： | TSB43AA82GGW |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PBGA176 |
| 封装： | PLASTIC, BGA-176 |
| 文件页数： | 142/146页 |
| 文件大小： | 770K |
| 代理商： | TSB43AA82GGW |
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83
0
1
2
3
4
5
6
7
8
9
10 11
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved
spd
tLabel
rt
tCode
prior
destination ID
destination_offset_high
destination_offset_low
data_length
extended_tCode
block data
Figure 82. DTF Packet Format With Block Data
Table 82. Block-Transmit Format Descriptions
FIELD NAME
DESCRIPTION
spd
This field indicates the speed at which this packet is to be sent. 00 = 100 Mbps, 01 = 200 Mbps, and 10 = 400 Mbps,
and 11 is undefined for this implementation.
tLabel
This field is the transaction label, which is a unique tag for each outstanding transaction between two nodes. This is
used to pair up a response packet with its corresponding request packet. This tLabel must be set to 01 xxxx , which is
block read request handling.
rt
This field in the retry code for this packet is:
00 = new
01 = retry_X
10 = retryA
11 = retryB
tCode
tCode is the transaction code for this packet (see Table 6-10 of IEEE 1394-1995 standard).
prior
This field is the priority level for this packet. For cable implementation, the value of the bits must be zero. For
backplane implementation, see clauses 5.4.1.3 and 5.4.2.1 of the IEEE 1394-1995 standard.
destination ID
This field is the concatenation of the 10-bit bus number and the 6-bit node number that forms the node address to
which this packet is being sent.
destination_offset_high,
destination_offset_low
The concatenation of these two fields addresses a quadlet in the destination node address space. This address must
be quadlet aligned (modulo 4). The upper four bits of the destination_offset_high field are used as the response code
for lock-response packets and the remaining bits are reserved.
data_length
The number of bytes of data to be transmitted in the packet
extended_tCode
The block extended_tCode to be performed on the data in this packet. See Table 6-11 of the IEEE 1394-1995
standard.
block Data
The data to be sent. If dataLength is 0, no data should be written into the DTF for this field. Regardless of the
destination or source alignment of the data, the first byte of the block must appear in byte 0 of the first quadlet.
8.3
Status Block Setup
TSB43AA82 can send status block packets to the initiator when the DMA successfully writes/reads the entire amount
of data. The contents of the status block packet should be loaded before starting the DMA transaction. This function
is active only when the DRFNotify bit at C0h and DTFNotify bit at B0h are set. Figure 83 shows the basic status block
format. Table 8-3 shows a description of each field.
0
1
2
3
4
5
6
7
8
9
10 11
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
AsAgent
Reserved
agent-
num
destination_offset_high
destination_offset_low
data_length
extended_tCode
status block
Figure 83. Status Block Format
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TSB43AA82GHH | 制造商:Texas Instruments 功能描述: |
| TSB43AA82I | 制造商:TI 制造商全称:Texas Instruments 功能描述:1394 INTEGRATED PHY AND LINK LAYER CONTROLLER |
| TSB43AA82IGGW | 功能描述:1394 接口集成电路 2Port Hi Perf Integ Phy&Link Layer Chip RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB43AA82PGE | 功能描述:1394 接口集成电路 2Port Hi Perf Integ Phy&Link Layer Chip RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB43AA82PGEG4 | 功能描述:1394 接口集成电路 2Port Hi Per Int Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
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