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参数资料
| 型号： | TSB43AA82GGW |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PBGA176 |
| 封装： | PLASTIC, BGA-176 |
| 文件页数： | 145/146页 |
| 文件大小： | 770K |
| 代理商： | TSB43AA82GGW |
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86
8-Bit Bulky
BDIF[2:0]
COMMENT
011
8-bit bulky mode
101
Reset
111
8-bit data of last block on packet
NOTES:
1. Any signal setting not included in the table is reserved.
2. Signal values should not be modified during data transfer.
16-Bit Bulky
BDIF[2:0]
COMMENT
000
8-bit data except last block on packet (lower)
010
16-bit bulky mode
011
8-bit bulky mode
100
8-bit data of last block on packet (lower)
110
16-bit data of last block on packet
101
Reset
111
8-bit data of last block on packet
NOTES:
1. Any signal setting not included in the table is reserved.
2. Signal values should not be modified during data transfer.
A written packet is automatically divided into the length specified by DTx header3, and is packetized.
Addresses specified on DTx header[1:2] are increased by the length of the data on each transmission. Also,
the last 3 bits of tLabel are incremented.
Each time an auto-divided packet transmission completes, DTAval is set and an appropriate
acknowledgement is displayed on DTxAck.
When a packetizer stops at the completion of all block data transmission or with some error, a DTFEnd
interrupt is created and its result is displayed on DTFSt(B0h).
8.4.2
Packet Receipt With DRF
By clearing the DRDSel bit on DMA control (90h), a packet stored in the DRF can be received. Data can not be read
with the DMA I/F in this case. When DRHStr in DMA control (90h) is set, the header of the packet is detached, and
the host reads only the data section with DRF data (ACh). The detached header is stored in DRF header[0:3]
(D0hDCh). When DRHStr is not set, the entire packet is read. The format for this is the same as reading from ARF.
Types of packets received by the DRF are:
Self-ID packet
Ordinary packet
Response packets to request packets from the DTF
Write request with specified address (direct mode)
Packetizer
Specified as a default
8.4.2.1 Self-ID Packet
Set both RXSId (08h, bit 1) and RSIsel (08h, bit 2) to 1 for the DRF to receive self-ID packets.
8.4.2.2 Response Packet to Request Packets From the DTF
To receive response packets to request packets from the DTF, set DTSpDis (90h, bit 7) to 0. This automatically sets
the expected values of the response packets. The DRF receives responses accordingly.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TSB43AA82GHH | 制造商:Texas Instruments 功能描述: |
| TSB43AA82I | 制造商:TI 制造商全称:Texas Instruments 功能描述:1394 INTEGRATED PHY AND LINK LAYER CONTROLLER |
| TSB43AA82IGGW | 功能描述:1394 接口集成电路 2Port Hi Perf Integ Phy&Link Layer Chip RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB43AA82PGE | 功能描述:1394 接口集成电路 2Port Hi Perf Integ Phy&Link Layer Chip RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB43AA82PGEG4 | 功能描述:1394 接口集成电路 2Port Hi Per Int Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
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