- 您现在的位置：买卖IC网 > PDF目录199479 > TSB43AA82GGW (TEXAS INSTRUMENTS INC) 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PBGA176 PDF资料下载
参数资料
| 型号： | TSB43AA82GGW |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PBGA176 |
| 封装： | PLASTIC, BGA-176 |
| 文件页数： | 78/146页 |
| 文件大小： | 770K |
| 代理商： | TSB43AA82GGW |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页当前第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页
311
3.4.7
Reserved at 1Ch
3.4.8
PHY Access Register at 20h
This register defaults to 0000 0000h and is unaffected by a bus reset.
BITS
ACRONYM
DIR
DESCRIPTION
0
RdPy
S/C
Read PHY bit. When RdPy is set to 1, the link sends a read register request with the address equal to
PhyRgAd to the PHY. This bit is cleared when the request is sent.
1
WrPy
S/C
Write PHY bit. When WrPy is set to 1, the link sends a write register request with the address equal to
PhyRgAd to the PHY. This bit is cleared when the request is sent.
23
Reserved
N/A
Reserved
47
PhyRgAd
R/W
PHY-register address. The address of the PHY register to be accessed when either WrPy or RdPy is 1.
815
PhyRgData
R/W
PHY-register data. The data to be written to the Phy register when WrPy is 1.
1619
Reserved
N/A
Reserved
2023
PhyRxAd
R/O
PHY-register-received address. The address of the PHY register from where PhyRxData came.
2431
PhyRxData
R/O
PHY-register-received data. The data of PHY register addressed by PhyRxAd.
3.4.9
Bus Reset Register at 24h
This register defaults to FFFF 003Fh and, except for the bits specified, is unaffected by a bus reset.
BITS
ACRONYM
DIR
DESCRIPTION
09
BusNumber
R/W
Bus number. The link uses BusNumber as BusID. When a bus reset completes, BusNumber is
automatically updated. The host can overwrite BusNumber. This field defaults to 3FFh and is unaffected
by a bus reset.
1015
NodeNum
R/O
Node number. The link uses NodeNum as NodeID. When a bus reset completes, NodeNum is set to an
appropriate value. This field defaults to 3Fh and is automatically set by the hardware after a bus reset.
1619
BRFErr_Code
R/O
Error code in bus reset. When a bus reset occurs, BRFErr_Code is set to the appropriate value. If
BRFErr_Code is not zero, the host initiates a bus reset again. The code table is below.
0000 No error
0001 Last self-ID port status is not all children, not the root node
0010 PHY ID is sequence error (not in the correct order)
0011 Inverted quadlet is not the reverse of preceding quadlet
0100 PHY ID sequence error (two gaps in PHY IDs)
0101 PHY ID sequence error (arbitration reset gap in PHY IDs)
0110 PHY ID within self-ID packet does not match
0111 Quadlet/inverted-quadlet sequence error
1000 First 2 bits of the self-ID packet do not match either 01 or 10
1001-1110 reserved
1111 At least one self-ID packet has different GAP count.
This field defaults to 0 and is automatically set by the hardware after a bus reset.
2025
NodeSum
R/O
Number of nodes in this 1394 topology. When a bus reset occurs, NodeSum is set to the appropriate value.
These bits default to 0 and are automatically set by the hardware after a bus reset.
2631
CFRContID
R/O
Node ID of isochronous resource manager. When a bus reset occurs, CFRContID is set to the appropriate
value. This field defaults to 3Fh and is automatically set by the hardware after a bus reset.
相关PDF资料 |
PDF描述 |
|---|---|
| TSB43DA42GHCR | PCI BUS CONTROLLER, PBGA196 |
| TSB500SK02 | 30 A, BARRIER STRIP TERMINAL BLOCK, 1 ROW, 1 DECK |
| TSB500SK10MDS | 30 A, BARRIER STRIP TERMINAL BLOCK, 1 ROW, 1 DECK |
| TSB5000331DS | 30 A, BARRIER STRIP TERMINAL BLOCK, 1 ROW, 1 DECK |
| TSB5000831 | 30 A, BARRIER STRIP TERMINAL BLOCK, 1 ROW, 1 DECK |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TSB43AA82GHH | 制造商:Texas Instruments 功能描述: |
| TSB43AA82I | 制造商:TI 制造商全称:Texas Instruments 功能描述:1394 INTEGRATED PHY AND LINK LAYER CONTROLLER |
| TSB43AA82IGGW | 功能描述:1394 接口集成电路 2Port Hi Perf Integ Phy&Link Layer Chip RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB43AA82PGE | 功能描述:1394 接口集成电路 2Port Hi Perf Integ Phy&Link Layer Chip RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB43AA82PGEG4 | 功能描述:1394 接口集成电路 2Port Hi Per Int Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
发布紧急采购，3分钟左右您将得到回复。