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| 型号： | TSX68C000MCB/C12.5A |
| 厂商： | E2V TECHNOLOGIES PLC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 12.5 MHz, MICROPROCESSOR, CDIP64 |
| 封装： | CERAMIC, SDIP-64 |
| 文件页数： | 28/54页 |
| 文件大小： | 901K |
| 代理商： | TSX68C000MCB/C12.5A |
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34
0853B–HIREL–09/07
TS68C000
e2v semiconductors SAS 2007
Notes:
1. If the asynchronous setup tlme (47) requirements are satisfied, the DTACK low-to-data setup time (31) requirement Gan be
ignored. The data must only satisfy the data-in to clock-low setup time (27) for the following cycle.
2. Where "CLKS" is stated as unit time limit, the relevant time in nanoseconds shall be calculated as the actual cycle time of
clock signal input multiply by the given number of CLKS limits.
3. For a loading capacitance of less than or equal to 50 picofarads, substrate 5 nanoseconds from the value given in the maxi-
mum columns.
4. Actual value depends on period.
5. If 47 is satisfied for bath DTACK and BERR, 48 may be 0 nanoseconds.
6. The processor will negate BG and begin driving the bus again if external arbitration logic negates BR before asserting
BGACK.
7. The falling edge of 56 triggers bath the negation of the strobes (AS, and X DS) and the falling edge of E. either of these
events can occur first depending upon the loading on each signal. Specification 49 indicates the absolute maximum skew
that will occur between the rising edge of the strobes and the falling edge of the E clock.
8. When AS and R/W are equally loaded (±20%), substrate 10 nanoseconds from the values in these columns.
9. Each terminal of the device under test shall be tested separately against all existing VCC and VSS terminals of the device
which shall be shorted together for the test. The other untested terminals shall be unconnected during the test. One cycle
10. This value should be treated as a min for design purpose. For the conformance testing the value shall be regarded as the
maximum time.
67
t
THL tTLH
(RH)
Transition time
HALT, RESET
input
Ref. 32
200
ns
69
t
w
(HRPW)
HALT and RESET
pulse width after
power up
Ref. 56
10
CLKS
70
t
PHL
(ASRV)
Propagation time
AS low
to R/W valid
Ref. 20A
420
20
ns
71
t
PHL
(FCVRL)
Propagation time
FC valid to R/W
low
Ref. 21A
4
60 (4)
50 (4)
30 (4)
ns
73
t
H
(CHDOI)
Hold time CLK
high to
Data-out
Ref. 53
40
0
ns
74
t
PLH tPHL
(RLDBO)
Propagation time
R/W low to Data-
bus impedance
change
Ref. 55
430
20
10
ns
75
t
PHL
(SHEL)
Propagation time
AS, DS low to E
low
Ref. 49
-70
+70
-55
+55
-45
+45
ns
76
t
H
(ELDOI)
Hold time E low to
Data-out
Ref. 54
430
20
15
ns
Table 2-9.
Additional Electrical Characteristics (Continued)
Item
NO.
Symbol
Parameter
Ref Number
Load
Number
TS68C000-8
TS68C000-10
TS68C000-12
Unit
Limits
Min
Max
Min
Max
Min
Max
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