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| 型号： | TSX68C000MCB/C12.5A |
| 厂商： | E2V TECHNOLOGIES PLC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 12.5 MHz, MICROPROCESSOR, CDIP64 |
| 封装： | CERAMIC, SDIP-64 |
| 文件页数： | 38/54页 |
| 文件大小： | 901K |
| 代理商： | TSX68C000MCB/C12.5A |
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43
0853B–HIREL–09/07
e2v semiconductors SAS 2007
TS68C000
Figure 2-13. EF6800 Interfacing Flowchart
2.7.6.1
Data Transfer Operation
Three signals on processor provide the EF 6800 interface. They are: enable (E), valid memory address
(VMA), and valid peripheral address (VPA). Enable corresponds to the E or phase 2 signal i n existing EF
6800 systems. The bus frequency is one tenth of the incoming TS68C000 clock frequency. The timing of
E allows 1 MHz peripherals to be used 8 MHz TS68C000. Enable has a 60/40 duty cycle, that is, it is low
for six input clocks and high for four input clocks. This duty cycle allows the processor to do successive
VPA accesses on successive E pulses.
EF6800 cycle timing is given in Figure 2-17 and Figure 2-18. At state zero (50) in the cycle, the address
bus is in the high-impedance state. A function code is asserted on the function code output fines. One-
half clock later, in state 1, the address bus is released from the high-impedance state.
During state 2, the address strobe (AS) is asserted to indicate that there Is a valid address on the
address bus. If the bus cycle is a read cycle, the upper and/or lower data strobes are also asserted in
state 2. If the bus cycle is a write cycle, the read/write (R/W) signal is switched to low (write) during state
2. One-half clock later, in state 3, the write data Is placed on the data bus, and in state 4 the data strobes
are issued to indicate valid data on the data bus. The processor now inserts wait states until it recog-
nizes the assertion of VPA.
The VPA input signals the processor that the address on the bus is the address of an EF 6800 device (or
an area reserved for EF6800 devices) and that the bus should conform to the phase 2 transfer charac-
teristics of the EF 6800 bus. Valid peripheral address is derived by decoding the address bus,
conditioned by the address strobe. Chip select for the EF 6800 peripherals should be derived by decod-
ing the address bus conditioned by VMA.
PROCESSOR
SLAVE
Initiate the cycle
1) The Processor Starts a Normal Read or Write Cycle
Synchronize with Enable
1) The Processor Monitors Enable (E) until it is low
(Phase 1)
2) The Processor Asserts Valid Memory Address (VMA)
Terminate the Cycle
1) The Processor waits until E goes low (on a read
cycle the data is latched as E goes low (internally)
2) The Processor negates VMA
3) The Processor negates AS, UDS and LDS
Start Next Cycle
Define EF 6800 Cycle
1) External Hardware Asserts Valid Peripheral
Address (VPA)
Transfer the Data
1) The Peripheral waits until E is active and then
transfers the Data
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