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| 型号： | TSX68C000MCB/C12.5A |
| 厂商： | E2V TECHNOLOGIES PLC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 12.5 MHz, MICROPROCESSOR, CDIP64 |
| 封装： | CERAMIC, SDIP-64 |
| 文件页数： | 39/54页 |
| 文件大小： | 901K |
| 代理商： | TSX68C000MCB/C12.5A |
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44
0853B–HIREL–09/07
TS68C000
e2v semiconductors SAS 2007
After recognition of VPA, the processor assures that the enable (E) is low, by waiting if necessary, and
subsequently asserts VMA. Valid memory address is then used as part of the chip select equation of the
peripheral. This ensures that the EF6800 peripherals are selected and deselected at the correct time.
The peripheral now runs its cycle during the high portion of the signal. Figure 2-17 and Figure 2-18
depict the best and worst case EF6800 cycle timing. This cycle length is dependent strictly upon when
VPA Is asserted in relationship to the E clock.
If it is assumed that external circuitry asserts VPA as soon as possible after the assertion of AS, then
VPA will be recognized as being asserted on the falling edge of 54. In this case, no "extra" wait cycles
will be inserted prior to the recognition of VPA asserted and only the wait cycles inserted to synchronize
with the E clock will determine the total length of the cycle. In any case, the synchronization delay will be
some integral number of clock cycles within the following two extremes:
1.
Best Case – VPA is recognized as being asserted on the falling edge three crack cycles before
E rizes (or three clock cycles after E falls).
2.
Worst Case – VPA is recognized as being asserted on the falling edge two clock cycles before E
rises (or four clock cycles after E falls).
During a read cycle, the processor latches the peripheral data in state 6. For all cycles, the processor
negates the address and data strobes one-half clack cycle rater in state 7 and the enable signal goes
low at this time. Another half clock later, the address bus is put in the high-impedance state. During a
write cycle the data bus is put in the high-impedance state and the read/write signal is switched high.
The peripheral logic must remove VPA within one clock after the address strobe is negated.
DTACK should not be asserted while VPA Is asserted. Notice that the TS68C000 VMA is active low, con-
strasted with the active high EF 6800 VMA. This allows the processor to put its buses in the high-
impedance state on DMA requests without inadvertently selecting the peripherals.
Figure 2-14. TS68C000 to EF6800 Peripheral Timing – Best Case
S0
S2
S4
w
ww
w
S6
S0
S2
CLK
A1-A23
AS
DTACK
Data Out
Data In
FC0-FC2
E
VPA
VMA
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